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Semiconductor Device with Linearly Restricted Gate Level Region Including Two Transistors of First Type and Two Transistors of Second Type with Offset Gate Contacts

Integrated Circuit Including Gate Electrode Level Region Including at Least Three Linear-Shaped Conductive Structures of Equal Length Having Aligned Ends and Positioned at Equal Pitch and Forming Multiple Gate Electrodes of Transistors of Different Type

Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length

Semiconductor Device Including at Least Six Transistor Forming Linear Shapes Including at Least Two Transistor Forming Linear Shapes Having Different Extension Distances Beyond Gate Contact

Semiconductor Device Including at Least Six Transistor Forming Linear Shapes with at Least Two Transistor Forming Linear Shapes Having Offset Ends