Patent Assignment
Reel/Frame 063424/0569
Patent Security Agreement
Recorded: 2023-04-21
Pages: 83
Assignor
RPX CORPORATION
Executed: 2021-07-06
Assignee
BARINGS FINANCE LLC, AS COLLATERAL AGENT
300 SOUTH TRYON STREET, SUITE 2500, CHARLOTTE, NORTH CAROLINA, 28202
Covered Properties
(316)
Method and Platform for Integrated Physical Verifications and Manufacturing Enhancements
PCT:
PCT/US2004/026832 ↗
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
PCT:
PCT/US2005/010267 ↗
Method and System for Topography-Aware Reticle Enhancement
PCT:
PCT/US2005/041923 ↗
Method and System for Finding an Equivalent Circuit Representation for One or More Elements in an Integrated Circuit
PCT:
PCT/US2005/046176 ↗
Methods for Creating Primitive Constructed Standard Cells
PCT:
PCT/US2006/025086 ↗
Dynamic Array Architecture
PCT:
PCT/US2007/006207 ↗
Integrated Circuit Cell Library for Multiple Patterning
PCT:
PCT/US2008/002884 ↗
Semiconductor Device with Dynamic Array Section
PCT:
PCT/US2008/009335 ↗
Methods, Structures and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
PCT:
PCT/US2008/011961 ↗
Super-Self-Aligned Contacts and Method for Making the Same
PCT:
PCT/US2008/086727 ↗
Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture
PCT:
PCT/US2009/036937 ↗
Circuitry and Layouts for Xor and Xnor Logic
PCT:
PCT/US2010/031650 ↗
Circuits with Linear Finfet Structures
PCT:
PCT/US2013/021345 ↗
Method and Platform for Integrated Physical Verifications and Manufacturing Enhancements
Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
Application:
10/820,260 →
Publication:
US 2005/0229130
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
Flexible Shape Identification for Optical Proximity Correction in Semiconductor Fabrication
Gate-Length Biasing for Digital Circuit Optimization
Patent:
7,441,211 →
Application:
11/145,025 →
Methods for Creating Primitive Constructed Standard Cells
Method and system for reshaping metal wires in VLSI design
Application:
11/199,900 →
Publication:
US 2007/0033558
Method and System for Finding an Equivalent Circuit Representation for One or More Elements in an Integrated Circuit
Method and System for Topography-Aware Reticle Enhancement
Method and System for Placing Layout Objects in a Standard-Cell Layout
System and Method for Varying the Starting Conditions for a Resolution Enhancement Program to Improve the Probability That Design Goals Will Be Met
Patent:
7,627,849 →
Application:
11/386,268 →
Method and System for Reshaping a Transistor Gate in an Integrated Circuit to Achieve a Target Objective
Patent:
7,730,432 →
Application:
11/391,771 →
Arrangement of Fill Unit Elements in an Integrated Circuit Interconnect Layer
Patent:
7,745,239 →
Application:
11/486,511 →
Layout Description Having Enhanced Fill Annotation
Patent:
7,676,772 →
Application:
11/486,936 →
Method and System for Wafer Topography-Aware Integrated Circuit Design Analysis and Optimization
Patent:
8,024,675 →
Application:
11/499,070 →
Method of Designing a Digital Circuit by Correlating Different Static Timing Analyzers
Patent:
7,823,098 →
Application:
11/590,581 →
Method and System for Integrated Circuit Optimization by Using an Optimized Standard-Cell Library
Patent:
7,716,612 →
Application:
11/602,043 →
Methods for Risk-Informed Chip Layout Generation
Patent:
7,590,968 →
Application:
11/680,552 →
Dynamic Array Architecture
Memory Timing Apparatus and Associated Methods
Patent:
7,586,800 →
Application:
11/836,088 →
Speculative Sense Enable Tuning Apparatus and Associated Methods
Patent:
7,577,049 →
Application:
11/836,099 →
Super-Self-Aligned Contacts and Method for Making the Same
Methods, Structures and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Semiconductor Device with Dynamic Array Section
Methods for Designing Semiconductor Device with Dynamic Array Section
Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same
Methods for Creating Primitive Constructed Standard Cells
Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (Pct) Application and Associated Methods
Integrated Circuit Cell Library for Multiple Patterning
System and Method for Performing Transistor-Level Static Performance Analysis Using Cell-Level Static Analysis Tools
Patent:
7,865,856 →
Application:
12/075,654 →
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
Gate-Length Biasing for Digital Circuit Optimization
Patent:
8,127,266 →
Application:
12/212,353 →
Dynamic Array Architecture
Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant
Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process
Application:
12/288,793 →
Publication:
US 2010/0107133
Methods and Systems for Process Compensation Technique Acceleration
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Methods for Defining Contact Grid in Dynamic Array Architecture
Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture
Methods for Multi-Wire Routing and Apparatus Implementing Same
Circuitry and Layouts for XOR and XNOR Logic
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
Oversized Contacts and Vias in Semiconductor Chip Defined by Linearly Constrained Topology
Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology
Optimizing Layout of Irregular Structures in Regular Layout Context
Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing Same
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
Semiconductor Device and Associated Layouts Including Linear Conductive Segments Having Non-Gate Extension Portions
Semiconductor Device and Associated Layouts Having Transistors Formed from Six Linear Conductive Segments with Intervening Diffusion Contact Restrictions
Semiconductor Device and Associated Layout Having Three or More Linear-Shaped Gate Electrode Level Conductive Segments of Both Equal Length and Equal Pitch
Semiconductor Device Having 1965 Nm Gate Electrode Level Region Including at Least Four Active Linear Conductive Segments and at Least One Non-Gate Linear Conductive Segment
Integrated Circuit and Associated Layout with Gate Electrode Level Portion Including at Least Two Complimentary Transistor Forming Linear Conductive Segments and at Least One Non-Gate Linear Conductive Segment
Semiconductor Device Having Linear-Shaped Gate Electrodes of Different Transistor Types with Uniformity Extending Portions of Different Lengths
Semiconductor Device and Associated Layouts Including Diffusion Contact Placement Restriction Based on Relation to Linear Conductive Segments
Semiconductor Device Having at Least Four Side-by-Side Gate Electrodes of Equal Length and Equal Pitch with at Least Two Transistor Connections to Power or Ground
Semiconductor Device Having Two Pairs of Transistors of Different Types Formed from Shared Linear-Shaped Conductive Features with Intervening Transistors of Common Type on Equal Pitch
Semiconductor Device and Associated Layouts Having Transistors Formed from Six Linear Conductive Segments with Gate Electrode-to-Gate Electrode Connection Through Single Interconnect Level and Common Node Connection Through Different Interconnect Level
Semiconductor Device and Associated Layouts Having Transistors Formed from Linear Conductive Segment with Non-Active Neighboring Linear Conductive Segment
Semiconductor Device and Associated Layouts Including Gate Electrode Level Region Having Arrangement of Six Linear Conductive Segments with Side-to-Side Spacing Less Than 360 Nanometers
Semiconductor Device Having at Least Three Linear-Shaped Electrode Level Conductive Features of Equal Length Positioned Side-by-Side at Equal Pitch
Integrated Circuit Device and Associated Layout Including Separated Diffusion Regions of Different Type Each Having Four Gate Electrodes with Each of Two Complementary Gate Electrode Pairs Formed from Respective Linear Conductive Segment
Integratd Circuit Device and Associated Layout Including Two Pairs of Co-Aligned Complementary Gate Electrodes with Offset Gate Contact Structures
Integrated Circuit Device and Associated Layout Including Linear Gate Electrodes of Different Transistor Types Next to Linear-Shaped Non-Gate Conductive Segment
Semiconductor Device and Associated Layouts Having Linear Shaped Gate Electrodes Defined Along at Least Five Adjacent Gate Electrode Tracks of Equal Pitch with Gate Electrode Connection Through Single Interconnect Level
Method for Fabricating Integrated Circuit with Gate Electrode Level Portion Including at Least Two Complementary Transistor Forming Linear Conductive Segments and at Least One Non-Gate Linear Conductive Segment
Semiconductor Device with Linearly Restricted Gate Level Region Including Two Transistors of First Type and Two Transistors of Second Type with Offset Gate Contacts
Integrated Circuit Device and Associated Layout Including Gate Electrode Level Region of 965 Nm Radius with Linear-Shaped Conductive Segments on Fixed Pitch
Integrated Circuit with Gate Electrode Level Region Including at Least Four Linear-Shaped Conductive Structures Forming Gate Electrodes of Transistors and Including Extending Portions of at Least Two Different Sizes
Integrated Circuit Including at Least Six Linear-Shaped Conductive Structures Forming Gate Electrodes of Transistors with at Least Two Linear-Shaped Conductive Structures of Different Length
Integrated Circuit Including at Least Six Linear-Shaped Conductive Structures Forming Gate Electrodes and Including Four Conductive Contacting Structures Having at Least Two Different Connection Distances
Integrated Circuit Including a Linear-Shaped Conductive Structure Forming One Gate Electrode and Having Length Greater Than or Equal to One-Half the Length of Linear-Shaped Conductive Structure Forming Two Gate Electrodes
Integrated Circuit Device with Linearly Defined Gate Electrode Level Region and Shared Diffusion Region of First Type Connected to Shared Diffusion Region of Second Type Through at Least Two Interconnect Levels
Integrated Circuit Device with Gate Electrode Level Region Including Two Side-by-Side Ones of at Least Three Linear-Shaped Conductive Structures Electrically Connected to Each Other Through Non-Gate Level
Method for Fabricating Integrated Circuit Having Three or More Linear-Shaped Gate Electrode Level Conductive Segments of Both Equal Length and Equal Pitch
Integrated Circuit Device with Gate Level Region Including Non-Gate Linear Conductive Segment Positioned Within 965 Nanometers of Four Transistors of First Type and Four Transistors of Second Type
Integrated Circuit Device with Gate Level Region Including at Least Three Linear-Shaped Conductive Segments Having Offset Line Ends and Forming Three Transistors of First Type and One Transistor of Second Type
Integrated Circuit Including Linear-Shaped Conductive Structures That Have Gate Portions and Extending Portions of Different Size
Methods of Fabricating and Creating Layout for Integrated Circuit Including at Least Six Linear-Shaped Conductive Structures Forming Gate Electrodes of Transistors with at Least Two Linear-Shaped Conductive Structures of Different Length
Semiconductor Device and Associated Layouts Having Linear Shaped Gate Electrodes Defined Along at Least Five Adjacent Gate Electrode Tracks of Equal Pitch
Method of Fabricating Integrated Circuit Including at Least Six Linear-Shaped Conductive Structures at Equal Pitch Including at Least Two Linear-Shaped Conductive Structures Having Non-Gate Portions of Different Length
Integrated Circuit Having Gate Electrode Level Region Including at Least Four Linear-Shaped Conductive Structures with Some Outer-Contacted Linear-Shaped Conductive Structures Having Larger Outer Extending Portion Than Inner Extending Portion
Integrated Circuit Including Gate Electrode Level Region Including at Least Seven Linear-Shaped Conductive Structures of Equal Length Positioned at Equal Pitch with at Least Two Linear-Shaped Conductive Structures Each Forming One Transistor and Having Extending Portion Sized Greater Than Gate Portion
Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
Integrated Circuit with Gate Electrode Level Including at Least Six Linear-Shaped Conductive Structures Forming Gate Electrodes of Transisters with at Least One Pair of Linear-Shaped Conductive Structures Having Offset Ends
Integrated Circuit Including Gate Electrode Level Region Including at Least Three Linear-Shaped Conductive Structures of Equal Length Having Aligned Ends and Positioned at Equal Pitch and Forming Multiple Gate Electrodes of Transistors of Different Type
Integrated Circuit Including Gate Electrode Level Region Including at Least Four Linear-Shaped Conductive Structures of Equal Length Having Aligned Ends and Positioned at Equal Pitch and Forming Multiple Gate Electrodes of Transistors of Different Type
Semiconductor Device with Gate Level Including Four Transistors of First Type and Four Transistors of Second Type Separated by Non-Diffusion Region with Restricted Gate Contact Placement Over Separating Non-Diffusion Region
Semiconductor Device with Linearly Restricted Gate Level Region Including Four Serially Connected Transistors of First Type and Four Serially Connected Transistors of Second Type Separated by Non-Diffusion Region
Semiconductor Device with Gate Level Including Four Transistors of First Type and Four Transistors of Second Type Separated by Non-Diffusion Region and Having at Least Two Gate Contacts Positioned Outside Separating Non-Diffusion Region
Semiconductor Device Including at Least Six Transistor Forming Linear Shapes Including at Least Two Different Gate Contact Connection Distances
Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length
Integrated Circuit Including at Least Three Linear-Shaped Conductive Structures of Different Length Each Forming Gate of Different Transistor
Semiconductor Device Including at Least Six Transistor Forming Linear Shapes Including at Least Two Transistor Forming Linear Shapes Having Different Extension Distances Beyond Gate Contact
Semiconductor Device and Associated Layouts Having Transistors Formed from Six Linear Conductive Segments with Gate Electrode Connection Through Single Interconnect Level
Method for Fabricating Integrated Circuit Having at Least Three Linear-Shaped Gate Electrode Level Conductive Features of Equal Length Positioned Side-by-Side at Equal Pitch
Method for Fabricating Integrated Circuit Including Separated Diffusion Regions of Different Type Each Having Four Gate Electrodes with Each of Two Complementary Gate Electrode Pairs Formed from Respective Linear Condcutive Segment
Integrated Circuit with Gate Electrode Level Region Including Multiple Linear-Shaped Conductive Structures Forming Gate Electrodes of Transistors and Including Uniformity Extending Portions of Different Size
Semiconductor Device Including Transistor Forming Linear Shapes Including Gate Portions and Extending Portions of Different Size
Integrated Circuit with Gate Electrode Level Including at Least Four Linear-Shaped Conductive Structures of Equal Length and Equal Pitch with Linear-Shaped Conductive Structure Forming One Transistor
Integrated Circuit Including at Least Six Linear-Shaped Conductive Structures Forming Gate Electrodes of Transistors with at Least Two Different Extension Distances Beyond Conductive Contacting Structures
Semiconductor Device with Gate Level Including Gate Electrode Conductors for Transistors of First Type and Transistor of Second Type with Some Gate Electrode Conductors of Different Length
Semiconductor Device with Gate Level Including Transistors of First Type and Transistors of Second Type with Corresponding Gate Contact Placement Restriction
Semiconductor Device with Linearly Restricted Gate Level Region Including Four Transistors of First Type and Four Transistors of Second Type with Gate Defining Shapes of Different Length
Method for Fabricating Integrated Circuit with Gate Electrode Level Region Including Two Side-by-Side Ones of at Least Three Linear-Shaped Conductive Structures Electrically Connected to Each Other Through Non-Gate Level
Integrated Circuit Including at Least Three Linear-Shaped Conductive Structures at Equal Pitch Including Linear-Shaped Conductive Structure Having Non-Gate Portion Length Greater Than Gate Portion Length
Integrated Circuit Including at Least Six Linear-Shaped Conductive Structive Structures at Equal Pitch Including at Least Two Linear-Shaped Conductive Structures Having Non-Gate Portions of Different Length
Semiconductor Device Including at Least Six Transistor Forming Linear Shapes with at Least Two Transistor Forming Linear Shapes Having Offset Ends
Methods for Gate-Length Biasing Using Annotation Data
Standard Cells Having Transistors Annotated for Gate-Length Biasing
Integrated Circuit Including Cross-Coupled Transistors Having Two Complementary Pairs of Co-Aligned Gate Electrodes with Offset Contacting Structures Positioned Between Transistors of Different Type
Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having at Least One Gate Contact Located Over Outer Portion of Gate Electrode Level Region
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within at Least Nine Gate Level Feature Layout Channels
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within at Least Twelve Gate Level Feature Layout Channels
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Electrical Connection of Cross- Coupled Transistors Through Same Interconnect Layer
Linear Gate Level Cross-Coupled Transistor Device with Non-Overlapping Pmos Transistors and Non-Overlapping Nmos Transistors Relative to Direction of Gate Electrodes
Integrated Circuit Including Cross-Coupled Transistors with Two Transistors of Different Type Having Gate Electrodes Formed by Common Gate Level Feature with Shared Diffusion Regions on Opposite Sides of Common Gate Level Feature
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Two Inside Positioned Gate Contacts and Two Outside Positioned Gate Contacts and Electrical Connection of Cross-Coupled Transistors Through Same Interconnect Layer
Integrated Circuit Including Cross-Coupled Trasistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Four Inside Positioned Gate Contacts Having Offset Relationships and Electrical Connection of Cross-Coupled Transistors Through Same I
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Four Inside Positioned Gate Contacts Having Offset and Aligned Relationships and Electrical Connection of Transistor Gates Through Li
Integrated Circuit Including Cross-Coupled Transistors with Two Transistors of Different Type Formed by Same Gate Level Structure and Two Transistors of Different Type Formed by Separate Gate Level Structures
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Four Inside Positioned Gate Contacts and Electrical Connection of Transistor Gates Through Linear Interconnect Conductors in Single I
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Four Inside Positioned Gate Contacts Having Offset and Aligned Relationships
Semiconductor Device Including Cross-Coupled Transistors Formed from Linear-Shaped Gate Level Features
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with at Least Two Different Gate Level Feature Extensions Beyond Contact
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Serially Connected Transistors
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with at Least Two Different Gate Level Feature Inner Extensions Beyond Gate Electrode
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Gate Contact Position Specifications
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with at Least Two Gate Electrodes Electrically Connected to Each Other Through Gate Level Feature
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature and Electrical Connection of Transistor Gates
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with at Least One Gate Level Feature Extending into Adjacent Gate Level Feature Layout Channel
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Level Feature Layout Channel Including Single Transistor
Integrated Circuit including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Outer Positioned Gate Contacts
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with at Least Two Gate Electrodes Electrically Connected to Each Other Through Another Transistor Forming Gate Level Feature
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Gate Contact Position and Offset Specifications
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Other Transistors Positioned Between Cross-Coupled Transistors
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Gate Contact Position, Alignment, and Offset Specifications
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels with Gate Electrode Placement Specifications
Cell Circuit and Layout with Linear Finfet Structures
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Methods for Cell Boundary Encroachment and Layouts Implementing the Same
Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same
Application:
12/981,151 →
Publication:
US 2011/0156167
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos
Methods for Designing Semiconductor Device with Dynamic Array Section
Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings
Methods for Multi-Wire Routing and Apparatus Implementing Same
Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits
Scalable Meta-Data Objects
Methods for linewidth modification and apparatus implementing the same
System and Method of Loading a Transaction Card and Processing Repayment on a Mobile Device
Coarse Grid Design Methods and Structures
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Integrated Circuit Including Cross-Coupled Transistors with Two Transistors of Different Type Having Gate Electrodes Formed by Common Gate Level Feature with Shared Diffusion Regions on Opposite Sides of Common Gate Level Feature
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Contact Position and Offset Specifications
Standard Cells having transistors annotated for gate-length biasing
Standard Cells Having Transistors Annotated for Gate-Length Biasing
Standard Cells Having Transistors Annotated for Gate-Length Biasing
Standard Cells Having Transistors Annotated for Gate-Length Biasing
System and Method for Processing Payment During an Electronic Commerce Transaction
Circuits with Linear Finfet Structures
Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature
Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings
Application:
13/774,919 →
Publication:
US 2013/0161760
Semiconductor Chip Including Gate Electrode Features Formed from Gate Electrode Feature Layout Shapes on Gate Horizontal Grid and Including First-Metal Features Formed from First-Metal Feature Layout Shapes on First-Metal Veritcal Grid
Application:
13/774,940 →
Publication:
US 2013/0168777
Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track
Application:
13/774,954 →
Publication:
US 2013/0168778
Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length
Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level
Integrated Circuit Including Linear Gate Electrode Structures Having Different Extension Distances Beyond Contact
Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks
Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks
Cross-Coupled Transistor Circuit Defined on Four Gate Electrode Tracks
Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts
Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track
Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer
Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks with Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track
Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with at Least Two Non-Inner Positioned Gate Contacts
Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends
Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact
Finfet Transistor Circuit
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Semiconductor Chip Including a Chip Level Based on a Layout That Includes Both Regular and Irregular Wires
Methods for Multi-Wire Routing and Apparatus Implementing Same
Super-Self-Aligned Contacts and Method for Making the Same
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Circuitry and Layouts for Xor and Xnor Logic
Coarse Grid Design Methods and Structures
Methods for Cell Boundary Encroachment and Layouts Implementing the Same
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Integrated Circuit Cell Library for Multiple Patterning
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration
Gate-Length Biasing for Digital Circuit Optimization
Standard Cells Having Transistors Annotated for Gate-Length Biasing
Semiconductor Chip Including Region Having Cross-Coupled Transistor Configuration with Offset Electrical Connection Areas on Gate Electrode Forming Conductive Structures and at Least Two Different Inner Extension Distances of Gate Electrode Forming Conductive Struc
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section
System and Method of Loading a Transaction Card and Processing Repayment on a Mobile Device
Methods for Multi-Wire Routing and Apparatus Implementing Same
Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods
Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods
Semiconductor Chip Including Digital Logic Circuit Including at Least Nine Linear-Shaped Conductive Structures Collectively Forming Gate Electrodes of at Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Metho
Scalable Meta-Data Objects
Super-Self-Aligned Contacts and Method for Making the Same
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Semiconductor Chip Including Digital Logic Circuit Including at Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods
Semiconductor Chip Including Region Having Integrated Circuit Transistor Gate Electrodes Formed by Various Conductive Structures of Specified Shape and Position and Method for Manufacturing the Same
System and Method of Processing Payment at a Point-of-Sale Terminal Using a Mobile Device
Application:
14/723,699 →
Publication:
US 2015/0339648
Semiconductor Chip Including Integrated Circuit Including Four Transistors of First Transistor Type and Four Transistors of Second Transistor Type with Electrical Connections Between Various Transistors and Methods for Manufacturing the Same
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
Application:
14/834,295 →
Publication:
US 2015/0363542
Methods for Linewidth Modification and Apparatus Implementing the Same
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
Semiconductor Chip Including Integrated Circuit Including At Least Five Gate Level Conductive Structures Having Particular Spatial and Electrical Relationship and Method for Manufacturing the Same
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same
Super-Self-Aligned Contacts and Method for Making the Same
System and Method of Loading a Transaction Card and Processing Repayment on a Mobile Device
Coarse Grid Design Methods and Structures
Methods for Multi-Wire Routing and Apparatus Implementing Same
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
Semiconductor Chip and Method for Manufacturing the Same
Application:
15/263,282 →
Publication:
US 2016/0379991
Semiconductor Chip and Method for Manufacturing the Same
Application:
15/344,452 →
Publication:
US 2017/0053937
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Application:
15/383,946 →
Publication:
US 2017/0098602
Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same
Application:
15/385,724 →
Publication:
US 2017/0104004
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
Cell Circuit and Layout with Linear Finfet Structures
Integrated Circuit Implementing Scalable Meta-Data Objects
Application:
15/452,364 →
Publication:
US 2017/0177779
Semiconductor Chip and Method for Manufacturing the Same
Application:
15/457,920 →
Publication:
US 2017/0186771
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section
Application:
15/457,997 →
Publication:
US 2017/0186772
Integrated Circuit Cell Library for Multiple Patterning
Circuitry and Layouts for Xor and Xnor Logic
Methods for Linewidth Modification and Apparatus Implementing the Same
Application:
15/646,825 →
Publication:
US 2017/0309609
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
Application:
15/651,801 →
Publication:
US 2017/0317064
System and Method for Processing Payment During an Electronic Commerce Transaction
Semiconductor Chip Including Region Having Rectangular-Shaped Gate Structures and First-Metal Structures
Optimizing Layout of Irregular Structures in Regular Layout Context
Application:
15/696,093 →
Publication:
US 2017/0365548
Semiconductor Cip Including Region Having Rectangular-Shaped Gate Structures and First Metal Structures
Semiconductor Chip Including Region Having Rectangular-Shaped Gate Structures and First Metal Structures
Methods for Multi-Wire Routing and Apparatus Implementing Same
Application:
15/724,252 →
Publication:
US 2018/0046745
Super-Self-Aligned Contacts and Method for Making the Same
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Application:
15/913,819 →
Publication:
US 2018/0196909
Coarse Grid Design Methods and Structures
Application:
15/919,884 →
Publication:
US 2018/0204795
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on First-Metal Vertical Grid
Application:
16/119,676 →
Publication:
US 2018/0374871
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on At Least Eight First-Metal Gridlines of First-Metal Vertical Grid
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on First-Metal Vertical Grid
Application:
16/119,757 →
Publication:
US 2019/0019810
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on At Least Eight First-Metal Gridlines of First-MetalVertical Grid
System and Method of Loading a Transaction Card and Processing Repayment on a Mobile Device
Cell Circuit and Layout with Linear Finfet Structures
Application:
16/593,459 →
Publication:
US 2020/0035663
Super-Self-Aligned Contacts and Method for Making the Same
Application:
16/667,750 →
Publication:
US 2020/0066722
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
Application:
16/890,643 →
Publication:
US 2020/0295044
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Application:
16/984,947 →
Publication:
US 2020/0381429
System and Method for Processing Payment During an Electronic Commerce Transaction
Application:
17/161,721 →
Publication:
US 2021/0256507
System and method for topography-aware reticle enhancement
Application:
60/630,072 →
System and method for calculation and use of equivalent shapes in the design of integrated circuits
Application:
60/640,917 →
System and method for introducing deliberate bias of suboptimality and error in the design and manufacture of integrated circuits
Application:
60/664,112 →
System and method for introducing deliberate nonuniformity of integrated-circuit transistor gate dimensions to reduce leakage currents
Application:
60/666,385 →
Gate-length biasing
Application:
60/678,694 →
System and method for standard-cell library optimization
Application:
60/755,722 →
Methods for risk-informed chip layout generation
Application:
60/778,236 →
Design independent system on chip implementation platform
Application:
60/781,288 →
Memory timing apparatus and associated methods
Application:
60/836,564 →
IC Cell Library with Pre-OPC/RET and Extra Layers for Design and Verification
Application:
60/890,819 →
Integrated Circuit Cell Library Suitable for Multiple Patterning
Application:
60/892,982 →
System and method for transistor-level timing using cell-level static timing analysis methods
Application:
60/906,443 →
Design independent system on chip implementation platform
Application:
60/963,364 →
Dynamic Array Architecture
Application:
60/972,394 →
Methods, Structures and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
Application:
60/983,091 →
Diffusion Variability Control and Transistor Device Sizing Using Hvt I/O Implant
Application:
60/988,762 →
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
Application:
61/024,980 →
Defining and Using Contact Grids in Circuit Using Dynamic Array Architecture
Application:
61/034,927 →
Cross-Coupled Transistor Layouts Using Linear Gate Level Features
Application:
61/036,460 →
Methods for Multi-Wire Routing and Apparatus Implementing Same
Application:
61/040,129 →
Cross-Coupled Transistor Layouts Using Linear Gate Level Features
Application:
61/042,709 →
Cross-Coupled Transistor Layouts Using Linear Gate Level Features
Application:
61/045,953 →
Cross-Coupled Transistor Layouts Using Linear Gate Level Features
Application:
61/050,136 →
Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology
Application:
61/059,712 →
Optimizing Layout of Irregular Structures in Regular Layout Context
Application:
61/060,090 →
Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing the Same
Application:
61/075,711 →
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
Application:
61/081,370 →
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
Application:
61/085,800 →
Methods and Systems for Process Compensation Technique Acceleration
Application:
61/087,546 →
Use of oversized contacts and vias in a linearly constrained topology
Application:
61/127,727 →
Circuitry and Layouts for XOR and XNOR Logic
Application:
61/174,408 →
Cell Layout and Scaling Using Linear Finfet Structures
Application:
61/176,058 →
Methods for Cell Boundary Encroachment and Layouts Implementing the Same
Application:
61/251,279 →
Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Implementation of the Same
Application:
61/291,212 →
Methods for Linewidth Modification and Apparatus Implementing the Same
Application:
61/413,284 →
Scalable Meta-Data Objects
Application:
61/420,313 →
Coarse Grid Design Methods and Structures
Application:
61/487,247 →
Circuits with Linear Finfet Structures
Application:
61/586,387 →
Circuits with Linear Finfet Structures
Application:
61/589,224 →
System and Method for Processing Payment During an Electronic Commerce Transaction
Application:
61/602,404 →
System and Method of Loading a Transaction Card and Processing Repayment on a Mobile Device
Application:
61/602,421 →
Gate-Length Biasing for Digital Circuit Optimization
Application:
95/001,832 →
Gate-Length Biasing for Digital Circuit Optimization
Application:
95/002,207 →
Methods for Gate-Length Biasing Using Annotation Data
Application:
95/002,214 →
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 8, 2014
From: BECKER, SCOTT T.
To: TELA INNOVATIONS, INC.
Reel/Frame 033689/0029 →
Release of Security Interest
Apr 12, 2021
From: SILICON VALLEY BANK
To: BLAZE DFM INC.
Reel/Frame 055899/0601 →
Release of Security Interest
Apr 12, 2021
From: VENTURE LENDING & LEASING IV, INC./VENTURE LENDING & LEASING V, INC.
To: TELA INNOVATIONS, INC.
Reel/Frame 055899/0604 →
Assignment of Assignor's Interest
Jun 7, 2021
From: TELA INNOVATIONS, INC.
To: RPX CORPORATION
Reel/Frame 056602/0001 →
Release of Lien on Patents
Aug 5, 2024
From: BARINGS FINANCE LLC
To: RPX CORPORATION
Reel/Frame 068328/0278 →
Patent Security Agreement
Aug 6, 2024
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 068328/0674 →