Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
View Patent ↗A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The gate electrodes include gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.
1. An integrated circuit, comprising:
a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent in a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature;
a plurality of interconnect level regions formed above the gate electrode level region; and
a first electrical connection defined to electrically connect the second gate level feature to the third gate level feature, the first electrical connection including a number of interconnect conductors located within one or more interconnect level regions of the plurality of interconnect level regions, wherein each of the number of interconnect conductors of the first electrical connection is linear-shaped.
2. An integrated circuit as recited in claim 1 , wherein the gate electrode level region includes a non-transistor gate level feature that does not form a gate electrode of a transistor and that is positioned between at least two other gate level features in the second direction.
3. An integrated circuit as recited in claim 2 , wherein a size of the non-transistor gate level feature as measured in the second direction is substantially equal to a size of at least one of the at least two other gate level features between which the non-transistor gate level feature is positioned.
4. An integrated circuit as recited in claim 1 , wherein each gate level feature has a substantially linear shape within the gate electrode level region.
5. An integrated circuit as recited in claim 4 , wherein the gate electrode level region includes a non-transistor gate level feature that does not form a gate electrode of a transistor and that is positioned between at least two other gate level features in the second direction.
6. An integrated circuit as recited in claim 5 , wherein the non-transistor gate level feature has a length as measured in the first direction substantially equal to a length of a gate level feature that forms gate electrodes of both a transistor of the first transistor type and a transistor of the second transistor type.
7. An integrated circuit as recited in claim 1 , wherein the first electrical connection extends in part through only one interconnect level region of the plurality of interconnect level regions.
8. An integrated circuit as recited in claim 7 , wherein the gate electrodes of the first and second transistors of the first transistor type are positioned according to a gate pitch defined as an equal center-to-center spacing measured in the second direction between adjacent gate electrodes, and
wherein the gate electrodes of the first and second transistors of the second transistor type are positioned according to the gate pitch.
9. An integrated circuit as recited in claim 8 , wherein all gate electrodes within the gate electrode level region are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.
10. An integrated circuit as recited in claim 9 , wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a second electrical connection that extends in part through a single interconnect level region of the plurality of interconnect level regions.
11. An integrated circuit as recited in claim 9 , wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a second electrical connection that extends through at least two interconnect level regions of the plurality of interconnect level regions.
12. An integrated circuit as recited in claim 9 , further comprising:
a first gate contact defined to physically contact the first gate level feature;
a second gate contact defined to physically contact the second gate level feature; and
a third gate contact defined to physically contact the third gate level feature,
wherein a position of the first gate contact is offset in the first direction from either a position of the second gate contact or a position of the third gate contact or positions of both the second and third gate contacts.
13. An integrated circuit as recited in claim 12 , wherein the gate electrode level region includes a given gate level feature that includes only one gate portion that forms a gate electrode of only one transistor of a given transistor type, the given gate level feature including an extension portion that extends away from its gate portion and over a non-diffusion region positioned between two diffusion regions of a diffusion type different than used to form the given transistor type.
14. An integrated circuit as recited in claim 13 , wherein the first gate level feature has a first extension distance beyond a location at which the first gate contact physically contacts the first gate level feature,
wherein the second gate level feature has a second extension distance beyond a location at which the second gate contact physically contacts the second gate level feature,
wherein the third gate level feature has a third extension distance beyond a location at which the third gate contact physically contacts the third gate level feature, and
wherein at least two of the first, second, and third extension distances are different.
15. An integrated circuit as recited in claim 1 , wherein the first electrical connection extends in part through only two interconnect level regions of the plurality of interconnect level regions.
16. An integrated circuit as recited in claim 15 , wherein the gate electrodes of the first and second transistors of the first transistor type are positioned according to a gate pitch defined as an equal center-to-center spacing measured in the second direction between adjacent gate electrodes, and
wherein the gate electrodes of the first and second transistors of the second transistor type are positioned according to the gate pitch.
17. An integrated circuit as recited in claim 16 , wherein all gate electrodes within the gate electrode level region are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.
18. An integrated circuit as recited in claim 17 , wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a second electrical connection that extends in part through a single interconnect level region of the plurality of interconnect level regions.
19. An integrated circuit as recited in claim 17 , wherein the shared diffusion region of the first diffusion type is electrically connected to the shared diffusion region of the second diffusion type through a second electrical connection that extends through at least two interconnect level regions of the plurality of interconnect level regions.
20. An integrated circuit as recited in claim 17 , further comprising:
a first gate contact defined to physically contact the first gate level feature;
a second gate contact defined to physically contact the second gate level feature; and
a third gate contact defined to physically contact the third gate level feature,
wherein a position of the first gate contact is offset in the first direction from either a position of the second gate contact or a position of the third gate contact or positions of both the second and third gate contacts.
21. An integrated circuit as recited in claim 20 , wherein the gate electrode level region includes a given gate level feature that includes only one gate portion that forms a gate electrode of only one transistor of a given transistor type, the given gate level feature including an extension portion that extends away from its gate portion and over a non-diffusion region positioned between two diffusion regions of a diffusion type different than used to form the given transistor type.
22. An integrated circuit as recited in claim 21 , wherein the first gate level feature has a first extension distance beyond a location at which the first gate contact physically contacts the first gate level feature,
wherein the second gate level feature has a second extension distance beyond a location at which the second gate contact physically contacts the second gate level feature,
wherein the third gate level feature has a third extension distance beyond a location at which the third gate contact physically contacts the third gate level feature, and
wherein at least two of the first, second, and third extension distances are different.
23. A method for creating a layout of an integrated circuit, comprising:
operating a computer to define a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature;
operating a computer to define a plurality of interconnect level regions formed above the gate electrode level region; and
operating a computer to define a first electrical connection to electrically connect the second gate level feature to the third gate level feature, the first electrical connection including a number of interconnect conductors located within one or more interconnect level regions of the plurality of interconnect level regions, wherein each of the number of interconnect conductors of the first electrical connection is linear-shaped.
24. A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:
program instructions for defining a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
wherein the second and third gate level features are located in different gate level feature layout channels,
wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature;
program instructions for defining a plurality of interconnect level regions formed above the gate electrode level region; and
program instructions for defining a first electrical connection to electrically connect the second gate level feature to the third gate level feature, the first electrical connection including a number of interconnect conductors located within one or more interconnect level regions of the plurality of interconnect level regions, wherein each of the number of interconnect conductors of the first electrical connection is linear-shaped.