Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings
An integrated circuit includes a first gate electrode feature of a first gate electrode track that forms a first n-channel transistor as it crosses an n-diffusion region, and a second gate electrode feature of the first gate electrode track that forms a first p-channel transistor as it crosses a p-diffusion region. The first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing. The integrated circuit includes a first gate electrode feature of a second gate electrode track that forms a second n-channel transistor as it crosses the n-diffusion region, and a second gate electrode feature of the second gate electrode track that forms a second p-channel transistor as it crosses the p-diffusion region. The first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing.
1 . An integrated circuit, comprising:
a first gate electrode feature of a first gate electrode track, wherein the first gate electrode feature of the first gate electrode track forms a first n-channel transistor as it crosses an n-diffusion region;
a second gate electrode feature of the first gate electrode track, wherein the second gate electrode feature of the first gate electrode track forms a first p-channel transistor as it crosses a p-diffusion region, wherein the first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing;
a first gate electrode feature of a second gate electrode track, wherein the first gate electrode feature of the second gate electrode track forms a second n-channel transistor as it crosses the n-diffusion region; and
a second gate electrode feature of the second gate electrode track, wherein the second gate electrode feature of the second gate electrode track forms a second p-channel transistor as it crosses the p-diffusion region, wherein the first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing such that a line of sight perpendicular to the first and second gate electrode tracks does not exist through the first and second end-to-end spacings.