Super-self-aligned contacts and method for making the same

1. A method for fabricating an active area contact within a semiconductor wafer, comprising:

forming a number of first hard mask portions over a corresponding number of underlying gate structures such that each first hard mask portion vertically shadows a respective one of the underlying gate structures;

forming a number of second hard mask filaments adjacent to each of the number of first hard mask portions such that a combined width of each first hard mask portion and its adjoining second hard mask filaments is greater than a width of the respective underlying gate structure, and such that a width of each second hard mask filament defines an active area contact-to-gate structure spacing;

etching a passage between facing surfaces of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area; and

depositing an electrically conductive material within the passage to form the active area contact.

2. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 1 , wherein each gate structure is configured as a linear gate structure having a top surface, substantially parallel side surfaces, a width defined perpendicularly between the side surfaces, and a length extending perpendicular to the width along the top surface, and wherein each gate structure is devoid of a substantial change in direction along its length.

3. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 1 , wherein the vertical shadowing of a given underlying gate structure by a given first hard mask portion is defined by the given first hard mask portion having a substantially same horizontal cross-section size and shape as the given underlying gate structure.

4. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 1 , further comprising:

depositing a photon absorption layer between the gate structures so as to substantially cover an area present between the gate structures with the photon absorption layer while leaving a top surface of each gate structure uncovered; and

depositing a dielectric layer over both the photon absorption layer and the top of each gate structure, wherein the number of first hard mask portions and the number of second hard mask filaments are formed on the dielectric layer.

5. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 4 , wherein forming the number of first hard mask portions over the corresponding number of underlying gate structures includes,

depositing a first hard mask layer over the dielectric layer,

depositing a negative photoresist layer over the first hard mask layer,

uniformly exposing the negative photoresist layer to vertically collimated incoherent light, whereby light is absorbed by the photon absorption layer and reflected by the top surface of the underlying gate structures so as to only cross-link negative photoresist portions that vertically overlie gate structures,

removing non-cross-linked negative photoresist such that negative photoresist portions that vertically overlie gate structures remain,

removing portions of the first hard mask layer that are not protected by the remaining negative photoresist portions, thereby forming the number of first hard mask portions, and

removing the remaining negative photoresist portions.

6. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 4 , wherein forming the number of second hard mask filaments adjacent to each of the number of first hard mask portions includes,

depositing a second hard mask layer over the dielectric layer and the number of first hard mask portions, and

removing portions of the second hard mask layer to leave a second hard mask filament adjacent to each side surface of each of the number of first hard mask portions.

7. A method for fabricating an active area contact within a semiconductor wafer as recited in claim 4 , wherein etching the passage includes,

depositing a positive photoresist layer over the dielectric layer, the number of first hard mask portions, and the number of second hard mask filaments,

patterning the positive photoresist layer to include a linear opening extending from one first hard mask portion to a neighboring first hard mask portion in a direction substantially perpendicular to each of the first hard mask portions, whereby a substantially rectangular area of the dielectric layer is exposed between neighboring second hard mask filaments in the linear opening, and

etching the passage downward through the rectangular area of the dielectric layer.

8. A method for fabricating a gate contact within a semiconductor wafer, comprising:

forming a first hard mask portion over a gate structure within a section of the semiconductor wafer, wherein the first hard mask portion vertically shadows the gate structure, and wherein the first hard mask portion includes substantially vertical side surfaces;

forming a second hard mask filament adjacent to each side surface of the first hard mask portion;

etching a passage through the first hard mask portion and through a depth of the semiconductor wafer to a top surface of the gate structure, whereby surfaces of the second hard mask filaments adjacent to the vertical side surfaces of the first hard mask portion are revealed through etching of the first mask portion and define side surfaces of the passage; and

depositing an electrically conductive material within the passage to form the gate contact.

9. A method for fabricating a gate contact as recited in claim 8 , wherein the vertical shadowing of the gate structure by the first hard mask portion is defined by the first hard mask portion having a substantially same horizontal cross-section size and shape as the gate structure.

10. A method for fabricating a gate contact as recited in claim 8 , further comprising:

depositing a photon absorption layer to fill regions adjacent to the gate structure so as to contact the gate structure without covering a top surface of the gate structure; and

depositing a dielectric layer over both the photon absorption layer and the gate structure, wherein the first hard mask portion and the second hard mask filaments are formed on the dielectric layer.

11. A method for fabricating a gate contact as recited in claim 10 , wherein forming the first hard mask portion over the gate structure includes,

depositing a first hard mask layer over the dielectric layer,

depositing a negative photoresist layer over the first hard mask layer,

uniformly exposing the negative photoresist layer to vertically collimated incoherent light, whereby light is absorbed by the photon absorption layer and reflected by the top surface of the gate structure so as to only cross-link a negative photoresist portion that vertically overlies the gate structure,

removing non-cross-linked negative photoresist such that only the negative photoresist portion that vertically overlies the gate structure remains,

removing portions of the first hard mask layer that are not protected by the remaining negative photoresist portion to form the first hard mask portion, and

removing the remaining negative photoresist portion.

12. A method for fabricating a gate contact as recited in claim 10 , wherein forming the second hard mask filament adjacent to each side surface of the first hard mask portion includes,

depositing a second hard mask layer over the dielectric layer and the first hard mask portion, and

removing portions of the second hard mask layer to leave a respective second hard mask filament adjacent to each side surface of the first hard mask portion.

13. A method for fabricating a gate contact as recited in claim 10 , wherein etching the passage includes,

depositing a positive photoresist layer over the dielectric layer, the first hard mask portion, and the second hard mask filaments,

patterning the positive photoresist layer to include a linear opening extending across the first hard mask portion and across portions of each second hard mask filament adjacent to the first hard mask portion, whereby a substantially rectangular area of the first hard mask portion is exposed between the portions of each second hard mask filament in the linear opening, and

etching the passage downward through the rectangular area of the first hard mask portion.

14. A method for fabricating a gate contact as recited in claim 13 , wherein an etching selectivity of the first hard mask portion is different from an etching selectivity of the second hard mask filaments, such that the first hard mask portion can be etched without substantially etching the second hard mask filaments.

15. A method for fabricating an active area contact and a gate contact within a semiconductor wafer, comprising:

depositing a photon absorption layer between gate structures within a section of the semiconductor wafer so as to substantially cover an area present between gate structures with the photon absorption layer while leaving a top surface of each gate structure uncovered;

depositing a dielectric layer over both the photon absorption layer and the top of each gate structure within the section of the semiconductor wafer;

forming a number of first hard mask portions on the dielectric layer and over the gate structures within the section of the semiconductor wafer, whereby each first hard mask portion vertically shadows a respective one of the gate structures, and wherein each first hard mask portion includes substantially vertical side surfaces;

forming a second hard mask filament adjacent to each vertical side surface of each first hard mask portion, each second hard mask filament having an exposed side surface, wherein a width of each second hard mask filament defines an active area contact-to-gate structure spacing;

etching a first passage between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area;

etching a second passage through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the gate structure underlying the given first hard mask portion, whereby surfaces of the second hard mask filaments adjacent to the vertical side surfaces of the given first hard mask portion are revealed through etching of the given first mask portion and define side surfaces of the second passage; and

depositing an electrically conductive material within both the first and second passages to respectively form the active area contact and the gate contact.

16. A method for fabricating an active area contact and a gate contact within a semiconductor wafer as recited in claim 15 , wherein the photon absorption layer is an amorphous carbon absorption layer.

17. A method for fabricating an active area contact and a gate contact within a semiconductor wafer as recited in claim 15 , wherein forming the number of first hard mask portions includes,

depositing a first hard mask layer over the dielectric layer, and

performing a photolithography process utilizing light absorption by the photon absorbing layer and light reflection by the top surface of each gate structure to form the number of first hard mask portions from the first hard mask layer.

18. A method for fabricating an active area contact and a gate contact within a semiconductor wafer as recited in claim 17 , wherein the photolithography process includes,

depositing a negative photoresist layer over the first hard mask layer,

uniformly exposing the negative photoresist layer to vertically collimated incoherent light, whereby light is absorbed by the photon absorption layer between gate structures and reflected by the top surface of each gate structure so as to only cross-link negative photoresist portions that vertically overlie the gate structures,

removing non-cross-linked negative photoresist such that only negative photoresist portions that vertically overlie the gate structures remain,

removing portions of the first hard mask layer that are not protected by the remaining negative photoresist portions to form the number of first hard mask portions, and

removing the remaining negative photoresist portions.

19. A method for fabricating an active area contact and a gate contact within a semiconductor wafer as recited in claim 15 , wherein etching the first passage includes,

depositing a positive photoresist layer over the dielectric layer, the first hard mask portions, and the second hard mask filaments,

patterning the positive photoresist layer to include a linear opening extending from one first hard mask portion to a neighboring first hard mask portion in a direction substantially perpendicular to each of the first hard mask portions, whereby a substantially rectangular area of the dielectric layer is exposed between neighboring second hard mask filaments in the linear opening, and

etching the first passage downward through the rectangular area of the dielectric layer.

20. A method for fabricating an active area contact and a gate contact within a semiconductor wafer as recited in claim 15 , wherein etching the second passage includes,

depositing a positive photoresist layer over the dielectric layer, the first hard mask portions, and the second hard mask filaments,

patterning the positive photoresist layer to include a linear opening extending across a given first hard mask portion and across portions of each second hard mask filament adjacent to the given first hard mask portion, whereby a substantially rectangular area of the given first hard mask is exposed between the portions of each second hard mask filament in the linear opening, and

etching the second passage downward through the rectangular area of the given first hard mask portion.