Cell circuit and layout with linear finfet structures
View Patent ↗A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.
1. An integrated circuit, comprising:
a substrate;
a first diffusion fin defined to extend over the substrate;
a first local interconnect structure formed to electrically connect the first diffusion fin to a first power line;
a second diffusion fin defined to extend over the substrate;
a second local interconnect structure formed to electrically connect the second diffusion fin to a second power line;
a third local interconnect structure formed to extend over and physically connect with each of the first diffusion fin and the second diffusion fin; and
a gate level structure formed to extend over and physically connect with each of the first diffusion fin and the second diffusion fin, the gate level structure positioned to physically connect with the first diffusion fin at a location between the first local interconnect structure and the third local interconnect structure, the gate level structure positioned to physically connect with the second diffusion fin at a location between the second local interconnect structure and the third local interconnect structure.
2. The integrated circuit as recited in claim 1 , wherein each of the first diffusion fin and the second diffusion fin is linear-shaped and is defined to extend lengthwise over the substrate in a first direction so as to extend parallel to each other.
3. The integrated circuit as recited in claim 2 , wherein the gate level structure is linear-shaped and is defined to extend lengthwise in a second direction perpendicular to the first direction.
4. The integrated circuit as recited in claim 3 , wherein the first local interconnect structure is linear-shaped and is defined to extend lengthwise in the second direction, and wherein the second local interconnect structure is linear-shaped and is defined to extend lengthwise in the second direction, and wherein the third local interconnect structure is linear-shaped and is defined to extend lengthwise in the second direction.
5. The integrated circuit as recited in claim 4 , wherein the gate level structure is substantially centered in the first direction between the first local interconnect structure and the third local interconnect structure.
6. The integrated circuit as recited in claim 5 , wherein the gate level structure is substantially centered in the first direction between the second local interconnect structure and the third local interconnect structure.
7. The integrated circuit as recited in claim 6 , further comprising:
a first contact structure positioned to provide electrical connection between the first local interconnect structure and the first power line.
8. The integrated circuit as recited in claim 7 , further comprising:
a second contact structure positioned to provide electrical connection between the second local interconnect structure and the second power line.
9. The integrated circuit as recited in claim 8 , further comprising:
a third contact structure positioned to provide electrical connection between the gate level structure and an interconnect structure positioned at a higher level than the gate level structure.
10. The integrated circuit as recited in claim 9 , wherein the first diffusion fin is a p-type diffusion fin, and wherein the second diffusion fin is an n-type diffusion fin.
11. The integrated circuit as recited in claim 9 , further comprising:
a third diffusion fin of linear shape, the third diffusion fin defined to extend lengthwise over the substrate in the first direction, wherein the first local interconnect structure is formed to physically contact each of the first diffusion fin and the third diffusion fin, and wherein the gate level structure is formed to physically contact each of the first diffusion fin and the third diffusion fin, and wherein the third local interconnect structure is formed to physically contact each of the first diffusion fin and the third diffusion fin.
12. The integrated circuit as recited in claim 11 , further comprising:
a fourth diffusion fin of linear shape, the fourth diffusion fin defined to extend lengthwise over the substrate in the first direction, wherein the second local interconnect structure is formed to physically contact each of the second diffusion fin and the fourth diffusion fin, and wherein the gate level structure is formed to physically contact each of the second diffusion fin and the fourth diffusion fin, and wherein the third local interconnect structure is formed to physically contact each of the second diffusion fin and the fourth diffusion fin.
13. The integrated circuit as recited in claim 12 , wherein a lengthwise centerline of the first diffusion fin is separated from a lengthwise centerline of the second diffusion fin by a diffusion fin pitch as measured in the second direction, and wherein a lengthwise centerline of the third diffusion fin is separated from the lengthwise centerline of the first diffusion fin by a first integer multiple of the diffusion fin pitch as measured in the second direction, and wherein a lengthwise centerline of the fourth diffusion fin is separated from the lengthwise centerline of the second diffusion fin by a second integer multiple of the diffusion fin pitch as measured in the second direction.
14. The integrated circuit as recited in claim 13 , wherein the first integer multiple is one and the second integer multiple is one.
15. The integrated circuit as recited in claim 13 , wherein the first integer multiple is two and the second integer multiple is one.
16. The integrated circuit as recited in claim 13 , wherein the first integer multiple is two and the second integer multiple is two.
17. The integrated circuit as recited in claim 13 , further comprising:
a fifth diffusion fin of linear shape, the fifth diffusion fin defined to extend lengthwise over the substrate in the first direction, wherein the first local interconnect structure is formed to physically contact the fifth diffusion fin, and wherein the gate level structure is formed to physically contact the fifth diffusion fin, and wherein the third local interconnect structure is formed to physically contact the fifth diffusion fin.
18. The integrated circuit as recited in claim 17 , further comprising:
a sixth diffusion fin of linear shape, the sixth diffusion fin defined to extend lengthwise over the substrate in the first direction, wherein the second local interconnect structure is formed to physically contact the sixth diffusion fin, and wherein the gate level structure is formed to physically contact the sixth diffusion fin, and wherein the third local interconnect structure is formed to physically contact the sixth diffusion fin.
19. The integrated circuit as recited in claim 18 , wherein a lengthwise centerline of the fifth diffusion fin is separated from the lengthwise centerline of the first diffusion fin by a third integer multiple of the diffusion fin pitch as measured in the second direction, and wherein a lengthwise centerline of the sixth diffusion fin is separated from the lengthwise centerline of the second diffusion fin by a fourth integer multiple of the diffusion fin pitch as measured in the second direction.
20. The integrated circuit as recited in claim 19 , wherein the first integer multiple is one, and the second integer multiple is one, and the third integer multiple is two, and the fourth integer multiple is two.