Method and platform for integrated physical verifications and manufacturing enhancements
View Patent ↗An automated design for manufacturability platform which provides integrated physical verification and manufacturing enhancement operations. The platform uses an efficient data structure capable of handling and manipulating both layout circuit and geometry characteristics, which permits a wide range of operations such as timing analysis, design-rule checking and optical proximity corrections on a single platform. This feature eliminates the need to translate layout representations between various tools without the requirement of using a common database. Moreover, the platform's common user interface enables encapsulated information exchange between the design and the manufacturing teams, permiting early consideration of manufacturing distortion or enhancement impact on circuit performance.
1. A computer-implemented method of generating a layout for an integrated circuit, the computer-implemented method comprising:
generating a layout based on a physical design of the integrated circuit;
performing a first circuit performance analysis on the layout;
incorporating manufacturing enhancements on the layout, the manufacturing enhancements including optical proximity correction;
performing a second circuit performance analysis on the layout using the layout with the manufacturing enhancements incorporated therein to generate a taped-out layout of the integrated circuit;
checking design-rules on the taped-out layout;
modifying the taped-out layout by performing the manufacturing enhancements on the taped-out layout using at least in part results of the first circuit performance analysis; and
performing a third circuit performance analysis on the modified taped-out layout with the manufacturing enhancements included therein to generate a final layout to be used in manufacturing of masks for fabrication of the integrated circuit.