Gate-length biasing for digital circuit optimization
View Patent ↗Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.
1. A method for preparing a layout used in making a semiconductor device, comprising:
identifying a transistor in a nominal layout that includes shape geometries usable in making of the semiconductor device, the identified transistor selected for gate-length biasing;
using an annotated layout to select the identified transistor, the annotated layout providing information defining gate-length biasing to be performed on the identified transistor of the nominal layout to produce the layout used in manufacturing when making the semiconductor device; and
producing a biased layout, the biased layout has a gate-length biased transistor resulting from the gate-length biasing defined using the information provided by the annotated layout, the method implemented by a processor executing a program;
wherein the information provided by the annotated layout itself identifies a modification of a gate length of the identified transistor in the nominal layout;
using the biased layout to manufacture the semiconductor device.
2. The method of claim 1 , wherein the annotated layout provides hints or markers to identify the transistor in the nominal layout that is to be processed for gate-length biasing.
3. The method of claim 1 , wherein the identifying includes identifying more than one transistor for gate-length biasing while not identifying certain transistors for gate-length biasing.
4. The method of claim 3 , wherein the gate-length biasing implements two or more gate lengths that are different than a nominal gate length found in the nominal layout.
5. The method of claim 1 , wherein using the annotated layout to produce the biased layout is at least partially executed by an electronic design automation (EDA) tool.
6. The method of claim 1 , wherein the information identifies transistors in the nominal layout that are to be optimized with both (a) gate-length biasing and (b) threshold voltage (V th ) value assignment.
7. A method for making a semiconductor device using an annotation layout, comprising,
obtaining the annotation layout that itself includes information describing a gate-length bias, the information itself identifying particular transistors in a nominal layout that are to be gate-length biased, wherein the information further defines an amount by which the particular transistors in the nominal layout are to be gate-length biased;
producing a biased layout, the biased layout has a gate-length biased transistor; and
fabricating at least one aspect of a finished semiconductor device using the biased layout, the method implemented by a processor executing a program.
8. The method of claim 7 , wherein the information identifies less than all transistors in the nominal layout.
9. The method of claim 7 , wherein the annotation layout includes information that allows the biased layout to pass rules of a design rule checker (DRC) tool.
10. The method of claim 7 , wherein the information in the annotation layout defines a modification in a shape of the particular transistors that are to be gate-length biased, the modification in shape includes an increased gate length or a reduction in gate length.
11. The method of claim 7 , wherein the information includes hints or markers to identify the particular transistors that are to be gate-length biased.
12. The method of claim 7 , wherein the information defines two or more gate lengths that are different than a nominal gate length found in the nominal layout.
13. The method of claim 7 , wherein the information is readable by an electronic design automation (EDA) tool.
14. The method of claim 7 , wherein the information additionally identifies a voltage threshold (V th ) value for particular transistors in the nominal layout.
15. The method of claim 14 , wherein the voltage threshold (V th ) value is identified for a transistor in the nominal layout that is also identified for gate length biasing.
16. The method of claim 7 , wherein the information references a size modification of the transistor that is a predefined fraction of a nominal gate length in the nominal layout.
17. The annotation layout of claim 16 , wherein the predefined fraction is 10% or less.
18. The method of claim 7 , wherein the transistors defined by the nominal layout includes transistors with at least two threshold voltages, and wherein one of the threshold voltages is a high or low voltage threshold (V th ) value.
19. The method of claim 7 , wherein the information identifies particular cells and particular transistors in cells, whether all or less than all of the transistors in particular cells are to be gate-length biased.
20. The method of claim 7 , wherein the information identifies transistors in the nominal layout that are to be optimized with both (a) gate-length biasing and (b) threshold voltage (V th ) value assignment.