Patent Assignment
Reel/Frame 022388/0032
Assignment of Assignor's Interest
Recorded: 2009-03-12
Received: 2009-03-12
Pages: 14
Assignor
BLAZE DFM INC.
Executed: 2009-03-12
Assignee
TELA INNOVATIONS, INC
655 CAMPBELL TECHNOLOGY PARKWAY, STE 150, CAMPBELL, CA, 95008, UNITED STATES
Covered Properties
(27)
Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process
Application:
12/288,793 →
Gate-Length Biasing for Digital Circuit Optimization
Application:
12/212,353 →
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
Application:
12/099,663 →
Piezoelectric-Based Toe-Heaters for Frostbite Protection
Application:
12/075,645 →
System and method for transistor-level timing using cell-level static timing analysis methods
Application:
60/906,443 →
Method and System for Integrated Circuit Optimization by Using an Optimized Standard-Cell Library
Application:
11/602,043 →
Method of Designing a Digital Circuit by Correlating Different Static Timing Analyzers
Application:
11/590,581 →
Method and System for Wafer Topography-Aware Integrated Circuit Design Analysis and Optimization
Application:
11/499,070 →
Arrangement of Fill Unit Elements in an Integrated Circuit Interconnect Layer
Application:
11/486,511 →
Layout Description Having Enhanced Fill Annotation
Application:
11/486,936 →
Method and System for Reshaping a Transistor Gate in an Integrated Circuit to Achieve a Target Objective
Application:
11/391,771 →
System and Method for Varying the Starting Conditions for a Resolution Enhancement Program to Improve the Probability That Design Goals Will Be Met
Application:
11/386,268 →
Method and System for Placing Layout Objects in a Standard-Cell Layout
Application:
11/331,605 →
System and method for standard-cell library optimization
Application:
60/755,722 →
Method and System for Topography-Aware Reticle Enhancement
Application:
11/267,686 →
Method and System for Finding an Equivalent Circuit Representation for One or More Elements in an Integrated Circuit
Application:
11/254,643 →
Method and system for reshaping metal wires in VLSI design
Application:
11/199,900 →
Gate-Length Biasing for Digital Circuit Optimization
Application:
11/145,025 →
System and method for introducing deliberate nonuniformity of integrated-circuit transistor gate dimensions to reduce leakage currents
Application:
60/666,385 →
Flexible Shape Identification for Optical Proximity Correction in Semiconductor Fabrication
Application:
11/089,723 →
System and method for introducing deliberate bias of suboptimality and error in the design and manufacture of integrated circuits
Application:
60/664,112 →
Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
Application:
11/074,882 →
System and method for calculation and use of equivalent shapes in the design of integrated circuits
Application:
60/640,917 →
System and method for topography-aware reticle enhancement
Application:
60/630,072 →
Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
Application:
10/820,260 →
Method for Correcting a Mask Design Layout
Application:
10/787,070 →
Method and Platform for Integrated Physical Verifications and Manufacturing Enhancements
Application:
10/643,799 →