IP Library › Patent Application 60664112
Patent Application Provisional Small
App. No. 60/664,112 · Confirmation No. 2453

System and method for introducing deliberate bias of suboptimality and error in the design and manufacture of integrated circuits

Provisional Application Expired
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 Code Description Pages PDF
2021-06-07 OATH Oath or Declaration filed 53 View
2005-03-21 TRNA Transmittal of New Application 2 View
2005-03-21 SPEC Specification 8 View
2005-03-21 DRW Drawings-only black and white line drawings 3 View
2005-03-21 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
60/664,112
Filed
2005-03-21