Intermediate layout for resolution enhancement in semiconductor fabrication
View Patent ↗Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
1. A computer-implemented method of performing resolution enhancement of a layout for an integrated circuit, the method comprising the steps of:
receiving a first intermediate resolution enhancement state layout including a plurality of first fragments and a plurality of first biases associated with the first fragments,
receiving a second intermediate resolution enhancement state layout including a plurality of second fragments and a plurality of second biases associated with the second fragments;
assembling the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout; and
by a computer, reconverging the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout by adjusting resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement to generate a third intermediate resolution enhancement state layout;
wherein the step of reconverging comprises determining an interacting neighborhood in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout, and adjusting the resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout only within the interacting neighborhood;
wherein the first intermediate resolution enhancement state layout includes an area of modification to the integrated circuit and the step of determining an interacting neighborhood comprises determining an area in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout within a halo radius from a center of the area of modification.
2. The computer-implemented method of claim 1 , wherein the resolution enhancement is adjusted according to a proximity to the center of the area of modification.
3. The computer-implemented method of claim 1 , wherein the step of adjusting the resolution enhancement comprises the step of damping the first biases and the second biases, the damping of the first biases and the second biases decaying linearly or exponentially with a distance from the center of the area of modification.
4. A computer program product including a non-transitory computer readable medium storing a computer program, the computer program, when executed by a computer, performs a method of performing resolution enhancement of a layout for an integrated circuit, the method comprising the steps of:
receiving a first intermediate resolution enhancement state layout including a plurality of first fragments and a plurality of first biases associated with the first fragments,
receiving a second intermediate resolution enhancement state layout including a plurality of second fragments and a plurality of second biases associated with the second fragments;
assembling the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout; and
reconverging the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout by adjusting resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout to generate a third intermediate resolution enhancement state layout;
wherein the step of reconverging comprises the steps of determining an interacting neighborhood in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout, and adjusting the resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout only within the interacting neighborhood;
wherein the first intermediate resolution enhancement state layout includes an area of modification to the integrated circuit and the step of determining an interacting neighborhood comprises determining an area in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout within a halo radius from a center of the area of modification.
5. The computer readable medium of claim 4 , wherein the resolution enhancement is adjusted according to a proximity to the center of the area of modification.
6. The computer readable medium of claim 4 , wherein the step of adjusting the resolution enhancement comprises the step of damping the first biases and the second biases, the damping of the first biases and the second biases decaying linearly or exponentially with a distance from the center of the area of modification.
7. A layout generation system comprising:
a memory module storing computer instructions configured to perform a method of generating a layout for an integrated circuit, the method comprising the steps of:
receiving a first intermediate resolution enhancement state layout including a plurality of first fragments and a plurality of first biases associated with the first fragments;
receiving a second intermediate resolution enhancement state layout including a plurality of second fragments and a plurality of second biases associated with the second fragments;
assembling the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout; and
reconverging the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout by adjusting resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout to generate a third intermediate resolution enhancement state layout; and
a processor module for executing the computer instructions;
wherein the step of reconverging comprises determining an interacting neighborhood in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout, and adjusting the resolution enhancement of the first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout only within the interacting neighborhood;
wherein the first intermediate resolution enhancement state layout includes an area of modification to the integrated circuit and the step of determining an interacting neighborhood comprises determining an area in the assembled first intermediate resolution enhancement state layout and the second intermediate resolution enhancement state layout within a halo radius from a center of the area of modification.
8. The layout generation system of claim 7 , wherein the resolution enhancement is adjusted according to a proximity to the center of the area of modification.
9. The layout generation system of claim 7 , wherein the step of adjusting the resolution enhancement comprises the step of damping the first biases and the second biases, the damping of the first biases and the second biases decaying linearly or exponentially with a distance from the center of the area of modification.