Layout description having enhanced fill annotation
View Patent ↗Computer readable media hosting a layout description of electric circuitry that includes a description of prospective fill units and includes characteristic data noting at least one characteristic of each fill unit. In one preferred embodiment, each prospective fill unit includes just a single prospective fill element. Also, in a preferred embodiment, said characteristic data includes effect on electrical characteristics of nearby electrical circuitry. These electrical characteristics may further include timing characteristics and capacitance characteristics. The effect on the thickness of nearby connective elements also may be noted.
1. A method of optimizing a chip layout section, comprising:
generating an initial version of a chip layout section to include a number of locked fill units and a number of shadow fill units, wherein the locked fill units are not removable from the chip layout section during integration of the chip layout section into an overall chip layout, and wherein the shadow fill units are removable from the chip layout section during integration of the chip layout section into the overall chip layout, wherein generating the initial version of the chip layout section includes generating an annotation of one or more electrical effects caused by each shadow fill unit, whereby the one or more electrical effects caused by a given shadow fill unit on a number of affected conductive features within the chip layout section is tabulated against the given shadow fill unit for each of the number of affected conductive features within the chip layout section, wherein evaluating the annotation is performed by a computer; and
evaluating the annotation of the one or more electrical effects caused by each shadow fill unit as tabulated within the initial version of the chip layout section to identify which of the number of shadow fill units are to be removed from the initial version of the chip layout section to generate an optimized version of the chip layout section;
removing the identified shadow fill units from the initial version of the chip layout section to generate the optimized version of the chip layout section.
2. The method of claim 1 , wherein evaluating the annotation of the one or more electrical effects caused by each shadow fill unit as tabulated within the initial version of the chip layout section is performed to improve timing characteristics of the number of affected conductive features within the chip layout section.
3. The method of claim 1 , wherein the initial version of the chip layout section identifies each of the number of locked fill units as locked and identifies each of the number of shadow fill units as shadow.
4. The method of claim 3 , wherein fill units near to an edge of the initial version of a chip layout section said first section are designated as shadow fill units.
5. The method of claim 4 , further comprising:
removing some of the shadow fill units near to the edge of the chip layout section to reduce a layout density near to the edge of the chip layout section so as to more closely match a layout density of a neighboring chip layout section.
6. The method of claim 1 , wherein generating an initial version of the chip layout section is performed by an outside vendor, and
wherein evaluating the annotation of the one or more electrical effects caused by each shadow fill unit, removing the identified shadow fill units from the initial version of the chip layout section to generate the optimized version of the chip layout section, and recording the optimized version of the chip layout section on the computer readable storage medium is performed by an integrated circuit integrator separate from the outside vendor.
7. The method of claim 1 , wherein the one or more electrical effects caused by the given shadow fill unit includes a signal timing impact on each of the number of affected conductive features and a parasitic impact on each of the number of affected conductive features.
8. The method of claim 1 , wherein the one or more electrical effects caused by the given shadow fill unit on a given affected conductive feature includes:
a percent effect on a speed of signal transmission on the given affected conductive feature,
an absolute change in time for a signal to be transmitted on the given affected conductive feature,
a change in capacitance on the given affected conductive feature,
a change in resistance on the given affected conductive feature,
a signal integrity impact on the given affected conductive feature,
a drop in voltage over a length of the given affected conductive feature,
a change in dynamic power of the given affected conductive feature,
a change in electromigration of the given affected conductive feature,
an inductance effect on the given affected conductive feature,
an effect on ground bounce on the given affected conductive feature,
an effect on power bounce on the given affected conductive feature,
or a combination thereof.
9. The method of claim 1 , wherein generating the initial version of the chip layout section includes generating an annotation of one or more physical effects caused by each shadow fill unit, whereby the one or more physical effects includes an effect on thickness of a chip area that includes the shadow fill unit.
10. The method of claim 9 , wherein the effect on thickness of the chip area that includes the shadow fill unit is defined as a function of distance from the shadow fill unit.
11. The method of claim 10 , wherein the effect on thickness of the chip area is defined as:
t=t o +{t δ *exp[(− c )*( d )]},
wherein t equals thickness of chip area, to equals thickness of chip area without the shadow fill unit, t δ equals change in thickness of the chip area relative to t o at a centerpoint of the shadow fill unit, d equals distance from the centerpoint of the shadow fill unit, and c equals a constant value.
12. The method of claim 1 , wherein the initial version of the chip layout section includes a suggested order of shadow fill unit removal.
13. The method of claim 1 , wherein the initial version of the chip layout section is represented in a GDS Stream Format, a Design Exchange Format, or an OASIS Format.