Methods for risk-informed chip layout generation

1. A method for generating a chip layout based on fabrication process capability, comprising:

selecting a minimum required value for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within a chip based on a balance between yield loss of the chip and size of the chip,

wherein the fabrication process is characterized by a measurable parameter, the measurable parameter having an associated distribution representing a frequency of occurrence of values of the parameter, the distribution being defined by a mean and a standard deviation, and

wherein the fabrication process capability factor represents a minimum fraction of a number of standard deviations that is between the mean of the parameter distribution and either a lower specification limit or an upper specification limit for the fabrication process;

determining design rules for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied;

generating a layout for the layer sub-region within the chip using the determined design rules associated with the layer sub-region; and recording the generated layout on a computer readable storage medium.

2. A method for generating a chip layout based on fabrication process capability as recited in claim 1 , further comprising:

selecting a value for the number of standard deviations; and

computing the fabrication process capability factor based on the selected value for the number of standard deviations, wherein a larger selected value for the number of standard deviations causes the determined design rules to be more restrictive.

3. A method for generating a chip layout based on fabrication process capability as recited in claim 1 , wherein the design rules for the layer sub-region are determined to constrain the fabrication process such that the parameter distribution corresponding to the constrained fabrication process enables the selected minimum required value for the fabrication process capability factor to be satisfied.

4. A method for generating a chip layout based on fabrication process capability as recited in claim 1 , further comprising:

determining a fabrication process capability factor associated with application of the determined design rules to the fabrication process; and

verifying that the selected minimum required value for the fabrication process capability factor is less than the determined fabrication process capability factor associated with application of the determined design rules to the fabrication process.

5. A method for generating a chip layout based on fabrication process capability as recited in claim 1 , wherein the generated layout for the layer sub-region and the determined design rules associated with the layer sub-region correspond to a linear design style.

6. A method for generating a chip layout based on fabrication process capability as recited in claim 5 , wherein the linear design style requires each feature in each layer sub-region within the chip to be linear in shape and positioned in a parallel orientation with respect to adjacent features within the same layer sub-region.

7. A method for generating a chip layout based on fabrication process capability as recited in claim 6 , wherein the features that are linear in shape extend in one direction without bending, the one direction being defined within a plane coincident with a layer of the chip.

8. A method for generating a chip layout based on fabrication process capability as recited in claim 6 , wherein a fixed separation distance is maintained between adjacent features within a given layer sub-region within the chip.

9. A method for generating a chip layout based on fabrication process capability as recited in claim 8 , wherein the fixed separation distance is defined to optimize photolithographic rendering of the features within the given layer sub-region.