Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same
A circuit is defined to operate in accordance with a common control signal. The circuit includes a plurality of transistors that have respective timing margins relative to the common control signal. Some of the plurality of transistors are defined differently from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof. The different definition of any given one of the plurality of transistors causes a reduction of either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a corresponding reduction in timing margin while maintaining a positive timing margin.
1 . A semiconductor device, comprising:
a circuit defined to operate in accordance with a common control signal, wherein the circuit includes a plurality of transistors that have respective timing margins relative to the common control signal, wherein some of the plurality of transistors are differentiated from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof, and
wherein the differentiation of any given one of the plurality of transistors is defined to reduce either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a correspondingly reduced timing margin that remains positive.
2 . A method for consumption of timing margin in an integrated circuit for reduce power utilization, comprising:
identifying a circuit defined to operate in accordance with a common control signal;
identifying a plurality of transistors within the circuit that have respective timing margins relative to the common control signal;
determining the respective timing margins of the plurality of transistors; and
defining some of the plurality of transistors differently from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof,
wherein the different definition of any given one of the plurality of transistors causes a reduction of either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a corresponding reduction in timing margin while maintaining a positive timing margin.