Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
View Patent ↗A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.
1. A method for fabricating an integrated circuit, comprising:
fabricating a substrate region that forms part of a substrate of the integrated circuit; and
fabricating a gate electrode level region above the substrate region, the gate electrode level region having a size of up to about 965 nanometers as measured in any direction parallel to the substrate region, wherein fabricating the gate electrode level region includes fabricating at least six linear-shaped conductive structures each formed to extend lengthwise in a first direction, the at least six linear-shaped conductive structures including—
a first linear-shaped conductive structure including a first gate portion that forms a gate electrode of a first transistor of a first transistor type and a second gate portion that forms a gate electrode of a first transistor of a second transistor type, the first linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the first linear-shaped conductive structure,
a second linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the first transistor type, the second linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the second linear-shaped conductive structure,
a third linear-shaped conductive structure including a gate portion that forms a gate electrode of a second transistor of the second transistor type, the third linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the third linear-shaped conductive structure,
a fourth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the first transistor type, the fourth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fourth linear-shaped conductive structure,
a fifth linear-shaped conductive structure including a gate portion that forms a gate electrode of a third transistor of the second transistor type, the fifth linear-shaped conductive structure also including a non-gate portion that extends in the first direction away from the gate portion of the fifth linear-shaped conductive structure,
a sixth linear-shaped conductive structure including a first gate portion that forms a gate electrode of a fourth transistor of the first transistor type and a second gate portion that forms a gate electrode of a fourth transistor of the second transistor type, the sixth linear-shaped conductive structure also including a non-gate portion that extends in the first direction between the first and second gate portions of the sixth linear-shaped conductive structure,
wherein the substrate region is fabricated to include a non-active region between transistors of the first transistor type and transistors of the second transistor type, wherein each non-gate portion of the first, second, third, fourth, fifth, and sixth linear-shaped conductive structures extends over the non-active region of the substrate region, and
wherein at least two of the non-gate portions of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
2. A method for fabricating an integrated circuit as recited in claim 1 , wherein fabricating the at least six linear-shaped conductive structures includes fabricating a seventh linear-shaped conductive structure that does not form a gate electrode of a transistor and that is positioned between at least two gate forming linear-shaped conductive structures that each form at least one gate electrode of at least one transistor, wherein a size of the seventh linear-shaped conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of one or more of the at least two gate forming linear-shaped conductive structures as measured in the second direction.
3. A method for fabricating an integrated circuit as recited in claim 1 , further comprising:
fabricating an interconnect level region above the substrate region, the interconnect level region fabricated to include a first linear-shaped conductive interconnect structure formed to extend lengthwise in a second direction perpendicular to the first direction.
4. A method for fabricating an integrated circuit as recited in claim 3 , wherein the interconnect level region is fabricated to include a second linear-shaped conductive interconnect structure formed to extend lengthwise in the second direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
5. A method for fabricating an integrated circuit as recited in claim 1 , wherein a length of the third linear-shaped conductive structure as measured in the first direction is greater than a length of the fifth linear-shaped conductive structure as measured in the first direction.
6. A method for fabricating an integrated circuit as recited in claim 5 , wherein the second linear-shaped conductive structure is substantially co-aligned with the third linear-shaped conductive structure along a common line of extent in the first direction.
7. A method for fabricating an integrated circuit as recited in claim 6 , wherein the fourth linear-shaped conductive structure is substantially co-aligned with the fifth linear-shaped conductive structure along a common line of extent in the first direction.
8. A method for fabricating an integrated circuit as recited in claim 7 , wherein a length of the second linear-shaped conductive structure as measured in the first direction is less than a length of the fourth linear-shaped conductive structure as measured in the first direction.
9. A method for fabricating an integrated circuit as recited in claim 8 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in a second direction perpendicular to the first direction, and wherein only the second, third, fourth, and fifth linear-shaped conductive structures are transistor gate-forming conductive structures within the gate electrode level region between the first and sixth linear-shaped conductive structures in the second direction.
10. A method for fabricating an integrated circuit as recited in claim 1 , wherein a length of the second linear-shaped conductive structure as measured in the first direction is less than a length of the fourth linear-shaped conductive structure as measured in the first direction.
11. A method for fabricating an integrated circuit as recited in claim 10 , wherein a length of the third linear-shaped conductive structure as measured in the first direction is greater than a length of the fifth linear-shaped conductive structure as measured in the first direction.
12. A method for fabricating an integrated circuit as recited in claim 11 , wherein the second linear-shaped conductive structure is substantially co-aligned with the third linear-shaped conductive structure along a common line of extent in the first direction.
13. A method for fabricating an integrated circuit as recited in claim 12 , wherein the fourth linear-shaped conductive structure is substantially co-aligned with the fifth linear-shaped conductive structure along a common line of extent in the first direction.
14. A method for fabricating an integrated circuit as recited in claim 13 , wherein each of the second, third, fourth, and fifth linear-shaped conductive structures is positioned between the first and sixth linear-shaped conductive structures in a second direction perpendicular to the first direction, and wherein only the second, third, fourth, and fifth linear-shaped conductive structures are transistor gate-forming conductive structures within the gate electrode level region between the first and sixth linear-shaped conductive structures in the second direction.
15. A method for fabricating an integrated circuit as recited in claim 1 , further comprising:
fabricating an interconnect level region formed above the substrate region, the interconnect level region fabricated to include a first linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction.
16. A method for fabricating an integrated circuit as recited in claim 15 , wherein the interconnect level region is fabricated to include a second linear-shaped conductive interconnect structure formed to extend lengthwise in the first direction, the second linear-shaped conductive interconnect structure positioned next to and spaced apart from the first linear-shaped conductive interconnect structure.
17. A method for fabricating an integrated circuit as recited in claim 16 , wherein each of the at least six linear-shaped conductive structures has a lengthwise centerline, the at least six linear-shaped conductive structures positioned according to a first equal centerline-to-centerline pitch as measured in a second direction perpendicular to the first direction, such that a distance as measured in the second direction between lengthwise centerlines of different ones of the at least six linear-shaped conductive structures is an integer multiple of the first equal centerline-to-centerline pitch, and
wherein the first and second linear-shaped conductive interconnect structures are positioned in a side-by-side manner according to a second equal centerline-to-centerline pitch as measured in the second direction, the second equal centerline-to-centerline pitch defined as a fractional multiple of the first equal centerline-to-centerline pitch.
18. A method for fabricating an integrated circuit as recited in claim 17 , further comprising:
fabricating a third linear interconnect conductive segment to extend lengthwise in the second direction perpendicular to the first direction.
19. A method for fabricating an integrated circuit as recited in claim 17 , further comprising:
fabricating at least one linear interconnect conductive segment to extend lengthwise in the second direction perpendicular to the first direction within a second interconnect level region above the substrate region.
20. A method for fabricating an integrated circuit as recited in claim 17 , wherein the second equal centerline-to-centerline pitch is less than or equal to the first equal centerline-to-centerline pitch.
21. A method for fabricating an integrated circuit as recited in claim 20 , wherein the fractional multiple of the first equal centerline-to-centerline pitch is one.
22. A method for fabricating an integrated circuit as recited in claim 21 , wherein the gate electrode level region is fabricated to include at least one non-gate forming linear-shaped conductive structure that does not form a gate electrode of a transistor.
23. A method for fabricating an integrated circuit as recited in claim 22 , wherein the at least one non-gate forming linear-shaped conductive structure is positioned in a side-by-side and spaced apart manner from an adjacently positioned linear-shaped conductive structure, and wherein a length of the at least one non-gate forming linear-shaped conductive structure as measured in the first direction is substantially equal to a length of the adjacently positioned linear-shaped conductive structure as measured in the first direction.
24. A method for fabricating an integrated circuit as recited in claim 1 , further comprising:
fabricating a first conductive contact structure to physically contact the second linear-shaped conductive structure, wherein the first conductive contact structure is positioned a first offset distance away from the gate portion of the second linear-shaped conductive structure, the first offset distance measured in the first direction;
fabricating a second conductive contact structure to physically contact the third linear-shaped conductive structure, wherein the second conductive contact structure is positioned a second offset distance away from the gate portion of the third linear-shaped conductive structure, the second offset distance measured in the first direction;
fabricating a third conductive contact structure to physically contact the fourth linear-shaped conductive structure, wherein the third conductive contact structure is positioned a third offset distance away from the gate portion of the fourth linear-shaped conductive structure, the third offset distance measured in the first direction; and
fabricating a fourth conductive contact structure to physically contact the fifth linear-shaped conductive structure, wherein the fourth conductive contact structure is positioned a fourth offset distance away from the gate portion of the fifth linear-shaped conductive structure, the fourth offset distance measured in the first direction,
wherein at least two of the first, second, third, and fourth offset distances are different.
25. A method for fabricating an integrated circuit as recited in claim 24 , further comprising:
fabricating an interconnect level region above the substrate region, wherein the third and fourth linear-shaped conductive structures are electrically connected to each other, and wherein an electrical connection between the third and fourth linear-shaped conductive structures includes one or more conductive interconnect structures located only within the interconnect level region.
26. A method for fabricating an integrated circuit as recited in claim 25 , wherein at least two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
27. A method for fabricating an integrated circuit as recited in claim 26 , wherein the gate electrode level region is fabricated to include at least one non-gate forming linear-shaped conductive structure that does not form a gate electrode of a transistor.
28. A method for fabricating an integrated circuit as recited in claim 27 , wherein the at least one non-gate forming linear-shaped conductive structure is positioned in a side-by-side and spaced apart manner from an adjacently positioned linear-shaped conductive structure, and wherein a length of the at least one non-gate forming linear-shaped conductive structure as measured in the first direction is substantially equal to a length of the adjacently positioned linear-shaped conductive structure as measured in the first direction.
29. A method for fabricating an integrated circuit as recited in claim 24 , wherein at least three of the first, second, third, and fourth offset distances are different.
30. A method for fabricating an integrated circuit as recited in claim 29 , wherein at least two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
31. A method for fabricating an integrated circuit as recited in claim 30 , wherein the gate electrode level region is fabricated to include at least one non-gate forming linear-shaped conductive structure that does not form a gate electrode of a transistor.
32. A method for fabricating an integrated circuit as recited in claim 31 , wherein the at least one non-gate foil ling linear-shaped conductive structure is positioned in a side-by-side and spaced apart manner from an adjacently positioned linear-shaped conductive structure, and wherein a length of the at least one non-gate forming linear-shaped conductive structure as measured in the first direction is substantially equal to a length of the adjacently positioned linear-shaped conductive structure as measured in the first direction.
33. A method for fabricating an integrated circuit as recited in claim 1 , wherein the second linear-shaped conductive structure is substantially co-aligned with the third linear-shaped conductive structure along a common line of extent in the first direction, and wherein the second linear-shaped conductive structure is separated from the third linear-shaped conductive structure by a first line end spacing distance, and
wherein the second linear-shaped conductive structure is electrically connected to the fifth linear-shaped conductive structure through one or more conductive structures located within a level of the integrated circuit other than a gate electrode level, wherein the gate electrode level includes the gate electrode level region.
34. A method for fabricating an integrated circuit as recited in claim 33 , wherein the second linear-shaped conductive structure is positioned within 360 nanometers of the fifth linear-shaped conductive structure.
35. A method for fabricating an integrated circuit as recited in claim 33 , wherein the first line end spacing distance is less than or equal to 240 nanometers.
36. A method for fabricating an integrated circuit as recited in claim 33 , wherein the fourth linear-shaped conductive structure is substantially co-aligned with the fifth linear-shaped conductive structure along a common line of extent in the first direction, and wherein the fourth linear-shaped conductive structure is separated from the fifth linear-shaped conductive structure by a second line end spacing distance, and
wherein the third linear-shaped conductive structure is electrically connected to the fourth linear-shaped conductive structure through one or more conductive structures located within a level of the integrated circuit other than a gate electrode level, wherein the gate electrode level includes the gate electrode level region.
37. A method for fabricating an integrated circuit as recited in claim 36 , wherein the second line end spacing distance is less than or equal to 240 nanometers.
38. A method for fabricating an integrated circuit as recited in claim 36 , wherein the first line end spacing distance is substantially equal to the second line end spacing distance.
39. A method for fabricating an integrated circuit as recited in claim 38 , wherein each of the first and second line end spacing distances is less than or equal to 240 nanometers.
40. A method for fabricating an integrated circuit as recited in claim 36 , wherein at least two of the second, third, fourth, and fifth linear-shaped conductive structures have different lengths as measured in the first direction.
41. A method for fabricating an integrated circuit as recited in claim 40 , wherein the gate electrode level region is fabricated to include at least one non-gate forming linear-shaped conductive structure that does not form a gate electrode of a transistor and that is positioned between at least two gate forming linear-shaped conductive structures that each form at least one gate electrode of at least one transistor, wherein a size of the non-gate forming linear-shaped conductive structure as measured in a second direction perpendicular to the first direction is substantially equal to a size of one or more of the at least two gate forming linear-shaped conductive structures as measured in the second direction.
42. A method for fabricating an integrated circuit as recited in claim 40 , wherein a first end of the first linear-shaped conductive structure is aligned in the first direction with a first end of the third linear-shaped conductive structure, and wherein the first end of the third linear-shaped conductive structure is aligned in the first direction with a first end of the fifth linear-shaped conductive structure.
43. A method for fabricating an integrated circuit as recited in claim 40 , wherein a first end of the first linear-shaped conductive structure is aligned in the first direction with a first end of the second linear-shaped conductive structure, and wherein the first end of the second linear-shaped conductive structure is aligned in the first direction with a first end of the fourth linear-shaped conductive structure.
44. A method for fabricating an integrated circuit as recited in claim 43 , wherein a second end of the first linear-shaped conductive structure is aligned in the first direction with a first end of the third linear-shaped conductive structure, and wherein the first end of the third linear-shaped conductive structure is aligned in the first direction with a first end of the fifth linear-shaped conductive structure.