Coarse grid design methods and structures
A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.
1. A semiconductor device, comprising:
a first linear-shaped gate level conductive structure having a length as measured in a first direction and a width as measured in a second direction perpendicular to the first direction, the first linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction;
a second linear-shaped gate level conductive structure having a length as measured in the first direction and a width as measured in the second direction, the second linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second linear-shaped gate level conductive structure separated from the lengthwise centerline of the first linear-shaped gate level conductive structure by a gate pitch as measured in the second direction, a portion of the second linear-shaped gate level conductive structure positioned next to a portion of the first linear-shaped gate level conductive structure;
a first contact structure formed to connect to the portion of the first linear-shaped gate level conductive structure that is positioned next to the portion of the second linear-shaped gate level conductive structure, wherein the first linear-shaped gate level conductive structure includes a first end section extending in the first direction beyond the first contact structure, wherein the first end section does not form part of a gate electrode of a transistor;
a second contact structure formed to connect to the portion of the second linear-shaped gate level conductive structure that is positioned next to the portion of the first linear-shaped gate level conductive structure; and
a linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the linear-shaped interconnect level conductive structure positioned to extend over and connect to both the first contact structure and the second contact structure.
2. The semiconductor device as recited in claim 1 , wherein the first end section extends a first distance as measured in the first direction beyond the first contact structure, wherein the second linear-shaped gate level conductive structure includes a first end section extending a second distance as measured in the first direction beyond the second contact structure, wherein the first distance is substantially equal to the second distance.
3. The semiconductor device as recited in claim 2 , wherein the first end section of the first linear-shaped gate level conductive structure and the first end section of the second linear-shaped gate level conductive structure are located on opposite sides of the linear-shaped interconnect level conductive structure relative to the first direction.
4. The semiconductor device as recited in claim 1 , further comprising:
a third linear-shaped gate level conductive structure having a length as measured in the first direction and a width as measured in the second direction, the third linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the third linear-shaped gate level conductive structure separated from the lengthwise centerline of the first linear-shaped gate level conductive structure by the gate pitch as measured in the second direction, a portion of the third linear-shaped gate level conductive structure positioned next to the first linear-shaped gate level conductive structure.
5. The semiconductor device as recited in claim 4 , wherein an entirety of the third linear-shaped gate level conductive structure is positioned next to the first linear-shaped gate level conductive structure.
6. The semiconductor device as recited in claim 4 , wherein the lengthwise centerline of the third linear-shaped conductive structure is substantially co-aligned with the lengthwise centerline of the second linear-shaped conductive structure.
7. The semiconductor device as recited in claim 6 , further comprising:
a third contact structure formed to connect to the third linear-shaped gate level conductive structure.
8. The semiconductor device as recited in claim 7 , wherein the third linear-shaped gate level conductive structure includes a first end section extending a third distance as measured in the first direction beyond the third contact structure and toward the second linear-shaped conductive structure.
9. The semiconductor device as recited in claim 8 , wherein the first linear-shaped gate level conductive structure includes a first end section extending a first distance as measured in the first direction beyond the first contact structure, wherein the second linear-shaped gate level conductive structure includes a first end section extending a second distance as measured in the first direction beyond the second contact structure, wherein the third distance is substantially equal to each of the first distance and the second distance.
10. The semiconductor device as recited in claim 8 , wherein the third linear-shaped gate level conductive structure is separated from the second linear-shaped conductive structure by a distance as measured in the first direction that is substantially equal to the width of the linear-shaped interconnect level conductive structure as measured in the first direction.
11. The semiconductor device as recited in claim 8 , wherein the third linear-shaped gate level conductive structure has an outer end opposite from the first end section of the third linear-shaped gate level conductive structure, and wherein the first linear-shaped gate level conductive structure has an outer end opposite from the first end section of the first linear-shaped gate level conductive structure, wherein the outer end of the third linear-shaped gate level conductive structure is substantially aligned with the outer end of the first linear-shaped gate level conductive structure at a same virtual line extending in the second direction.
12. The semiconductor device as recited in claim 7 , wherein a centerpoint of the third contact structure is separated from a centerpoint of the second contact structure by a distance as measured in the first direction that is substantially equal to two times an interconnect structure pitch, and wherein the linear-shaped interconnect level conductive structure has a lengthwise centerline oriented in the second direction that is substantially vertically aligned with the centerpoint of the second contact structure.
13. The semiconductor device as recited in claim 12 , wherein the linear-shaped interconnect level conductive structure is a first linear-shaped interconnect level conductive structure, the semiconductor device including a second linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the second linear-shaped interconnect level conductive structure positioned to extend over and connect to the third contact structure, wherein the second linear-shaped interconnect level conductive structure has a lengthwise centerline oriented in the second direction that is substantially vertically aligned with the centerpoint of the third contact structure.
14. The semiconductor device as recited in claim 13 , further comprising:
a third linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the third linear-shaped interconnect level conductive structure having a lengthwise centerline oriented in the second direction that is substantially centered between the lengthwise centerline of the first linear-shaped interconnect level conductive structure and the lengthwise centerline of the second linear-shaped interconnect level conductive structure.
15. The semiconductor device as recited in claim 13 , further comprising:
a fourth linear-shaped gate level conductive structure having a length as measured in the first direction and a width as measured in the second direction, the fourth linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the fourth linear-shaped gate level conductive structure separated from the lengthwise centerline of the second linear-shaped gate level conductive structure by the gate pitch as measured in the second direction, a portion of the fourth linear-shaped gate level conductive structure positioned next to the second linear-shaped gate level conductive structure.
16. The semiconductor device as recited in claim 15 , wherein an entirety of the fourth linear-shaped gate level conductive structure is positioned next to the second linear-shaped gate level conductive structure.
17. The semiconductor device as recited in claim 15 , wherein the lengthwise centerline of the fourth linear-shaped conductive structure is substantially co-aligned with the lengthwise centerline of the first linear-shaped conductive structure.
18. The semiconductor device as recited in claim 17 , further comprising:
a fourth contact structure formed to connect to the fourth linear-shaped gate level conductive structure.
19. The semiconductor device as recited in claim 18 , wherein the fourth linear-shaped gate level conductive structure includes a first end section extending a fourth distance as measured in the first direction beyond the fourth contact structure and toward the first linear-shaped conductive structure.
20. The semiconductor device as recited in claim 19 , wherein the first linear-shaped gate level conductive structure includes a first end section extending a first distance as measured in the first direction beyond the first contact structure, wherein the second linear-shaped gate level conductive structure includes a first end section extending a second distance as measured in the first direction beyond the second contact structure, wherein the third linear-shaped gate level conductive structure includes a first end section extending a third distance as measured in the first direction beyond the third contact structure and toward the second linear-shaped conductive structure, wherein the fourth distance is substantially equal to each of the first distance and the second distance and the third distance.
21. The semiconductor device as recited in claim 19 , wherein the fourth linear-shaped gate level conductive structure is separated from the first linear-shaped conductive structure by a distance as measured in the first direction that is substantially equal to the width of the first linear-shaped interconnect level conductive structure as measured in the first direction.
22. The semiconductor device as recited in claim 19 , wherein the fourth linear-shaped gate level conductive structure has an outer end opposite from the first end section of the fourth linear-shaped gate level conductive structure, and wherein the second linear-shaped gate level conductive structure has an outer end opposite from the first end section of the second linear-shaped gate level conductive structure, wherein the outer end of the fourth linear-shaped gate level conductive structure is substantially aligned with the outer end of the second linear-shaped gate level conductive structure at a same virtual line extending in the second direction.
23. The semiconductor device as recited in claim 18 , wherein a centerpoint of the fourth contact structure is separated from a centerpoint of the first contact structure by a distance as measured in the first direction that is substantially equal to two times the interconnect structure pitch.
24. The semiconductor device as recited in claim 23 , further comprising:
a third linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the third linear-shaped interconnect level conductive structure positioned to extend over and connect to the fourth contact structure, wherein the third linear-shaped interconnect level conductive structure has a lengthwise centerline oriented in the second direction that is substantially vertically aligned with the centerpoint of the fourth contact structure.
25. The semiconductor device as recited in claim 24 , further comprising:
a fourth linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the fourth linear-shaped interconnect level conductive structure having a lengthwise centerline oriented in the second direction that is substantially centered between the lengthwise centerline of the first linear-shaped interconnect level conductive structure and the lengthwise centerline of the third linear-shaped interconnect level conductive structure.
26. A method for manufacturing a semiconductor device, comprising:
forming a first linear-shaped gate level conductive structure having a length as measured in a first direction and a width as measured in a second direction perpendicular to the first direction, the first linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction;
forming a second linear-shaped gate level conductive structure having a length as measured in the first direction and a width as measured in the second direction, the second linear-shaped gate level conductive structure having a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second linear-shaped gate level conductive structure separated from the lengthwise centerline of the first linear-shaped gate level conductive structure by a gate pitch as measured in the second direction, a portion of the second linear-shaped gate level conductive structure positioned next to a portion of the first linear-shaped gate level conductive structure;
forming a first contact structure formed to connect to the portion of the first linear-shaped gate level conductive structure that is positioned next to the portion of the second linear-shaped gate level conductive structure, wherein the first linear-shaped gate level conductive structure includes a first end section extending in the first direction beyond the first contact structure, wherein the first end section does not form part of a gate electrode of a transistor;
forming a second contact structure formed to connect to the portion of the second linear-shaped gate level conductive structure that is positioned next to the portion of the first linear-shaped gate level conductive structure; and
forming a linear-shaped interconnect level conductive structure having a length as measured in the second direction and a width as measured in the first direction, the linear-shaped interconnect level conductive structure positioned to extend over and connect to both the first contact structure and the second contact structure.