Methods and systems for process compensation technique acceleration
View Patent ↗Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium.
1. A method for accelerating process compensation technique (PCT) processing of a semiconductor chip layout, comprising:
operating a computer to replace selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, wherein each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image;
following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, operating a computer to perform a chip-wide PCT processing operation on the semiconductor chip layout for a given chip level; and
operating a computer to record the chip-wide PCT processed semiconductor layout for the given chip level on a computer readable storage medium.
2. A method as recited in claim 1 , wherein the chip-wide PCT processing operation on the semiconductor chip layout for the given chip level is perfolined without PCT processing of the PCT pre-processed cells present within the semiconductor chip layout.
3. A method as recited in claim 1 , wherein the chip-wide PCT processing operation on the semiconductor chip layout for the given chip level includes PCT processing of the PCT pre-processed cells present within the semiconductor chip layout.
4. A method as recited in claim 3 , wherein the chip-wide PCT processing of a given PCT pre-processed cell considers the PCT-based cell layout adjustments already present in the given PCT pre-processed cell.
5. A method as recited in claim 1 , further comprising:
specifying one or more PCT pre-processed cells in the semiconductor chip layout for PCT processing during the chip-wide PCT processing operation; and
PCT processing the one or more specified PCT pre-processed cells in the semiconductor chip layout during the chip-wide PCT processing operation, wherein non-specified PCT pre-processed cells in the semiconductor chip layout are not subjected to PCT processing during the chip-wide PCT processing operation.
6. A method as recited in claim 1 , wherein the selected cells in the semiconductor chip layout that are replaced by corresponding PCT pre-processed cells are standard cells.
7. A method as recited in claim 1 , wherein the selected cells in the semiconductor chip layout that are replaced by corresponding PCT pre-processed cells are non-memory cells.
8. A method as recited in claim 1 , wherein the persistent storage medium is a computer readable medium.
9. A method as recited in claim 1 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include an optical proximity correction (OPC) processing operation.
10. A method as recited in claim 1 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include both an optical proximity correction (OPC) processing operation and a mask proximity correction (MPC) operation.
11. A method for processing a semiconductor chip layout for fabrication, comprising:
a) obtaining a chip layout having a number of cells placed in a section of the chip layout to form a prescribed integrated circuit;
b) operating a computer to replace one or more of the number of placed cells with a corresponding process compensation technique (PCT) pre-processed cell, wherein a given PCT pre-processed cell represents a particular placed cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments within the given PCT pre-processed cell, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image;
c) operating a computer to perform a chip-wide PCT processing operation on a given level of the chip layout to generate a chip-wide PCT processed chip layout for the given level;
d) operating a computer to record the chip-wide PCT processed chip layout for the given level on a computer readable storage medium; and
e) repeating operations c) and d) for each level of the chip that requires PCT processing for fabrication.
12. A method as recited in claim 11 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include an optical proximity correction (OPC) processing operation.
13. A method as recited in claim 11 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include both an optical proximity correction (OPC) processing operation and a mask proximity correction (MPC) operation.
14. A method as recited in claim 11 , wherein the number of cells placed in the section of the chip layout to form the prescribed integrated circuit are standard cells.
15. A method as recited in claim 11 , wherein the number of cells placed in the section of the chip layout to form the prescribed integrated circuit are non-memory cells.
16. A method as recited in claim 11 , wherein the chip-wide PCT processed chip layout is recorded in a digital format on a computer readable storage medium.
17. A method as recited in claim 11 , wherein the operations a) through e) are performed by computer executable program instructions stored on a computer readable medium and executed by a computer.
18. A method as recited in claim 11 , wherein the chip-wide PCT processing of operation c) is performed without PCT processing of the PCT pre-processed cells within the chip layout.
19. A method as recited in claim 11 , wherein the chip-wide PCT processing of operation c) includes PCT processing of the PCT pre-processed cells within the chip layout, and wherein the PCT processing of a given PCT pre-processed cell within the chip layout begins with the PCT-based cell layout adjustments present within the given PCT pre-processed cell.
20. A method as recited in claim 11 , further comprising:
prior to operation c), specifying one or more PCT pre-processed cells in the chip layout for PCT processing during the chip-wide PCT processing of operation c); and
during operation c), PCT processing the one or more specified PCT pre-processed cells in the chip layout, wherein the PCT processing of a given PCT pre-processed cell within the chip layout begins with the PCT-based cell layout adjustments present within the given PCT pre-processed cell, and wherein non-specified PCT pre-processed cells in the chip layout are not subjected to PCT processing during the chip-wide PCT processing of operation c).
21. A process compensation technique (PCT) processing system, comprising:
an input module defined to receive a chip layout for PCT processing, wherein the chip layout includes a number of cells placed in a section of the chip layout to form a prescribed integrated circuit;
a cell substitution module defined to replace one or more of the number of cells in the chip layout with a corresponding PCT pre-processed cell, wherein a given PCT pre-processed cell represents a particular cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments within the given PCT pre-processed cell, wherein the cell-level-PCT processing operation of a given cell includes generation of at least one as-fabricated aerial image of one or more PCT processed levels of the given cell and evaluation of PCT processing adequacy based on the at least one as-fabricated aerial image;
a PCT processing module defined to perform a chip-wide PCT processing operation on specified levels of the chip layout to generate a chip-wide PCT processed chip layout for each of the specified levels of the chip layout; and
an output module defined to record the chip-wide PCT processed chip layout for each of the specified levels of the chip layout on a persistent storage medium.
22. A system as recited in claim 21 , wherein the PCT processing module is defined to perform the chip-wide PCT processing operation without PCT processing of the PCT pre-processed cells within the chip layout.
23. A system as recited in claim 21 , wherein the PCT processing module is defined to PCT process the PCT pre-processed cells within the chip layout during the chip-wide PCT processing operation, and wherein the PCT processing of a given PCT pre-processed cell within the chip layout begins with the PCT-based cell layout adjustments present within the given PCT pre-processed cell.
24. A system as recited in claim 21 , wherein the PCT processing module is defined to PCT process tagged PCT pre-processed cells during the chip-wide PCT processing operation, and wherein the PCT processing of a given tagged PCT pre-processed cell within the chip layout begins with the PCT-based cell layout adjustments present within the given tagged PCT pre-processed cell, and
wherein during the chip-wide PCT processing operation the PCT processing module is defined to skip PCT processing of non-tagged PCT pre-processed cells in the chip layout.
25. A system as recited in claim 21 , further comprising:
a cell library accessible by the cell substitution module, wherein the cell library includes PCT pre-processed cells for use by the cell substitution module in replacing one or more of the number of cells in the chip layout.
26. A system as recited in claim 21 , wherein the input module, the cell substitution module, the PCT processing module, and the output module are defined as either software, firmware, hardware, or a combination thereof.
27. A system as recited in claim 21 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include an optical proximity correction (OPC) processing operation.
28. A system as recited in claim 21 , wherein both the cell-level-PCT-processing operation and the chip-wide PCT processing operation include both an optical proximity correction (OPC) processing operation and a mask proximity correction (MPC) operation.
29. A system as recited in claim 21 , wherein the chip-wide PCT processed chip layout is recorded in a digital format on a computer readable storage medium.