Patent Assignment
Reel/Frame 029862/0367
Assignment of Assignor's Interest
Recorded: 2013-02-22
Pages: 5
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Methods, Systems, and Articles of Manufacture for Implementing Full-Chip Optimization with Reduced Physical Design Data