Patent Assignment
Reel/Frame 030516/0639
Assignment of Assignor's Interest
Recorded: 2013-05-30
Pages: 2
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77 R.O.C., TAIWAN
Covered Property
(1)
Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells