Patent Assignment
Reel/Frame 030825/0400
Assignment of Assignor's Interest
Recorded: 2013-07-18
Pages: 5
Assignor
RPX CORPORATION
Executed: 2013-07-03
Assignee
HTC CORPORATION
NO. 23, XINGHUA RD., TAOYUAN CITY, TAOYUAN COUNTY, 330, TAIWAN
Covered Properties
(31)
Adapter for Computer Interface
Patent:
5,540,601 →
Application:
08/220,075 →
Scb Array External to a Host Adapter Integrated Circuit
Patent:
5,625,800 →
Application:
08/269,491 →
Disk System with Headerless Track Format, Embedded Servo Fields and Constant Density Recording
Patent:
5,715,106 →
Application:
08/324,298 →
System for Transferring 32-Bit Double Word Ide Data Sequentially Without an Intervening Instruction by Automatically Incrementing I/O Port Address and Translating Incremented Address
Patent:
5,802,392 →
Application:
08/504,921 →
Hardware Alignment in a Headerless Disk Drive Architecture
Patent:
5,802,584 →
Application:
08/522,639 →
Logical and Physical Zones for Management of Defects in a Headerless Disk Drive Architecture
Patent:
5,812,755 →
Application:
08/522,687 →
System and Method for Encoding and Decoding Data Using Numerical Computations in Galois Fields
Patent:
5,787,099 →
Application:
08/542,277 →
Use of a Stored Signal to Switch Between Memory Banks
Patent:
5,913,924 →
Application:
08/574,534 →
System and Method for Co-Planar and Nearly Co-Planar Printed Circuit Board Extension Docking System
Patent:
5,853,297 →
Application:
08/666,076 →
Method for Determining Whether Bi-Directional or Unidirectional Data Line Circuits Are Used
Patent:
5,821,798 →
Application:
08/709,501 →
Dual Edge D Flip Flop
Patent:
5,793,236 →
Application:
08/766,892 →
Integrated Circuit Test Stimulus Verification and Vector Extraction System
Patent:
5,920,490 →
Application:
08/773,386 →
Enhanced Dual Port I/O Bus Bridge
Patent:
6,044,207 →
Application:
08/821,783 →
Data Sector Mark Generation for a Headerless Disk Drive Architecture
Patent:
5,940,862 →
Application:
08/823,779 →
Bus to Bus Bridge Deadlock Prevention System
Patent:
5,889,972 →
Application:
08/823,958 →
Integrated Circuit Design for Single Ended Receiver Margin Tracking
Patent:
5,831,472 →
Application:
08/829,051 →
Design Verification System Using Expect Buffers
Patent:
5,937,182 →
Application:
08/829,316 →
System for Aligning Control Words for Identifying Boundaries of Headerless Data Sectors Using Automatic Incrementing and Discarding of Data Frame Numbers
Patent:
6,000,018 →
Application:
08/877,115 →
Hot-Switchable Scsi Controller Having Output Drivers with Quick Turn-On
Patent:
5,919,253 →
Application:
08/882,198 →
Method and Apparatus for Controlling Clock Skew in an Integrated Circuit
Patent:
5,828,870 →
Application:
08/884,863 →
Object Oriented Simulation Modeling
Patent:
5,923,867 →
Application:
08/903,803 →
Method and Apparatus for Performing Error Correction Code Operations
Patent:
6,041,431 →
Application:
08/933,568 →
Mechanism for Incremental Backup of on-Line Files
Patent:
6,101,585 →
Application:
08/963,905 →
Method and System for Changing Peripheral Component Interconnect Configuration Registers
Patent:
5,948,076 →
Application:
09/001,615 →
Method and Apparatus for Allocating Exclusive Shared Resource Requests in a Computer System
Patent:
6,105,094 →
Application:
09/013,498 →
Intentionally Mismatched Mirror Process Inverse Current Source
Patent:
5,939,933 →
Application:
09/023,395 →
Pipelined Berlekamp-Massey Error Locator Polynomial Generating Apparatus and Method
Patent:
6,092,233 →
Application:
09/046,117 →
An Integrated Circuit Scsi I/O Cell Having Signal Assertion Edge Triggered Timed Glitch Filter That Defines a Strobe Masking Period to Protect the Contents of Data Latches
Patent:
6,055,587 →
Application:
09/049,365 →
Redundant Bus Bridge Systems and Methods Using Separately-Powered Bus Bridges
Patent:
6,154,802 →
Application:
09/062,278 →
Timer Using a Single Counter to Track Multiple Time-Outs
Patent:
6,002,737 →
Application:
09/089,054 →
Communications Interface Adapter for a Computer System Including Posting of System Interrupt Status
Patent:
6,085,278 →
Application:
09/089,068 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 2, 2012
From: HUPPER ISLAND LLC
To: RPX CORPORATION
Reel/Frame 028142/0922 →
Merger
Aug 6, 2013
From: FUTURE DOMAIN CORPORATION
To: POWER I/O, INC.
Reel/Frame 030947/0323 →
Merger
Aug 6, 2013
From: DISTRIBUTED PROCESSING TECHNOLOGY CORP.
To: ADAPTEC, INC.
Reel/Frame 030947/0813 →
Merger
Aug 6, 2013
From: POWER I/O, INC.
To: ADAPTEC, INC.
Reel/Frame 030966/0792 →
Change of Name
Aug 6, 2013
From: ADAPTEC, INC.
To: ADPT CORPORATION
Reel/Frame 030966/0867 →
Change of Name
Aug 6, 2013
From: ADAPTEC, INC.
To: ADPT CORPORATION
Reel/Frame 030967/0033 →
Assignment of Assignor's Interest
Aug 8, 2014
From: HTC CORPORATION
To: 8631654 CANADA INC.
Reel/Frame 033493/0466 →
Merger and Change of Name
Jun 28, 2017
From: 8631654 CANADA INC.; QUARTERHILL INC.
To: QUARTERHILL INC.
Reel/Frame 043027/0098 →
Assignment of Assignor's Interest
Jul 21, 2017
From: QUARTERHILL INC.
To: WI-LAN INC.
Reel/Frame 043285/0115 →