Patent Assignment
Reel/Frame 028142/0922
Assignment of Assignor's Interest
Recorded: 2012-05-02
Pages: 18
Assignor
HUPPER ISLAND LLC
Executed: 2012-04-20
Assignee
RPX CORPORATION
ONE MARKET PLAZA, STEUART TOWER, SUITE 700, SAN FRANCISCO, CALIFORNIA, 94105
Covered Properties
(212)
Integrated Crystal Oscillator with Circuit for Limiting Crystal Power Dissipation
Patent:
5,150,081 →
Application:
07/662,530 →
Integrated Circuit Chip Core Logic System Controller with Power Saving Features for a Microcomputer System
Patent:
5,390,350 →
Application:
07/689,358 →
Packaging for Populated Circuit Boards
Patent:
5,195,302 →
Application:
07/779,701 →
Page Mode Buffer Controller for Transferring Nb Byte Pages Between a Host and Buffer Memory Without Interruption Except for Refresh
Patent:
5,551,054 →
Application:
07/795,161 →
Intelligent Hardware for Automatically Controlling Buffer Memory Storage Space in a Disk Drive
Patent:
5,450,546 →
Application:
07/830,041 →
Method and Structure for Locating and Skipping Over Servo Bursts on a Magnetic Disk
Patent:
5,592,348 →
Application:
08/145,037 →
Intelligent Hardware for Automatically Reading and Writing Multiple Sectors of Data Between a Computer Bus and a Disk Drive
Patent:
5,768,617 →
Application:
08/153,560 →
Adapter for Computer Interface
Patent:
5,540,601 →
Application:
08/220,075 →
Scb Array External to a Host Adapter Integrated Circuit
Patent:
5,625,800 →
Application:
08/269,491 →
Time Domain Signal Filter
Patent:
5,587,686 →
Application:
08/300,284 →
Method and Apparatus for Automatically Loading Configuration Data on Reset into a Host Adapter Integrated Circuit
Patent:
5,727,207 →
Application:
08/301,463 →
Synchronization Circuit for Clocked Signals of Similar Frequencies
Patent:
5,729,719 →
Application:
08/301,510 →
Disk System with Headerless Track Format, Embedded Servo Fields and Constant Density Recording
Patent:
5,715,106 →
Application:
08/324,298 →
Servo Burst Controller for a Magnetic Disk
Patent:
5,612,834 →
Application:
08/454,907 →
Synchronization Circuit for Clocked Signals of Similar Frequencies
Patent:
5,684,982 →
Application:
08/465,031 →
System for Transferring 32-Bit Double Word Ide Data Sequentially Without an Intervening Instruction by Automatically Incrementing I/O Port Address and Translating Incremented Address
Patent:
5,802,392 →
Application:
08/504,921 →
Programmable Data Transfer Without Sector Pulses in a Headerless Disk Drive Architecture
Patent:
5,812,335 →
Application:
08/522,037 →
Hardware Alignment in a Headerless Disk Drive Architecture
Patent:
5,802,584 →
Application:
08/522,639 →
Logical and Physical Zones for Management of Defects in a Headerless Disk Drive Architecture
Patent:
5,812,755 →
Application:
08/522,687 →
System and Method for Solving Quadratic Equation in Galois Fields
Patent:
5,771,184 →
Application:
08/542,198 →
Arithmetic Logic Unit and Method for Numerical Computations in Galois Fields
Patent:
5,812,438 →
Application:
08/542,262 →
System and Method for Encoding and Decoding Data Using Numerical Computations in Galois Fields
Patent:
5,787,099 →
Application:
08/542,277 →
Use of a Stored Signal to Switch Between Memory Banks
Patent:
5,913,924 →
Application:
08/574,534 →
Digital Delay Circuit and Method
Patent:
5,789,969 →
Application:
08/617,994 →
Method and Apparatus for Generating Addresses
Patent:
5,956,757 →
Application:
08/620,266 →
Hard Disk Format Using Frames of Sectors to Optimize
Patent:
5,627,946 →
Application:
08/636,296 →
Sequencer Map for a Hard Disk Controller Combining Data and Next-Address Fields
Patent:
5,596,737 →
Application:
08/639,257 →
System and Method for Co-Planar and Nearly Co-Planar Printed Circuit Board Extension Docking System
Patent:
5,853,297 →
Application:
08/666,076 →
Method for Determining Whether Bi-Directional or Unidirectional Data Line Circuits Are Used
Patent:
5,821,798 →
Application:
08/709,501 →
Dual Edge D Flip Flop
Patent:
5,793,236 →
Application:
08/766,892 →
Integrated Circuit Test Stimulus Verification and Vector Extraction System
Patent:
5,920,490 →
Application:
08/773,386 →
Format Calculator for Headerless Hard Disk with Embedded Servo Wedges
Patent:
5,959,795 →
Application:
08/808,099 →
Method of Managing Hardware Control Blocks Utilizing Endless Queue Maintained to Never Be Empty and Containing Tail Pointer Only Accessible by Process Executing on System Processor
Patent:
6,006,292 →
Application:
08/815,645 →
Improved Hardware Command Block Delivery Queue for Host Adapters and Other Devices with Onboard Processors
Patent:
5,938,747 →
Application:
08/816,980 →
Enhanced Dual Port I/O Bus Bridge
Patent:
6,044,207 →
Application:
08/821,783 →
Data Sector Mark Generation for a Headerless Disk Drive Architecture
Patent:
5,940,862 →
Application:
08/823,779 →
Bus to Bus Bridge Deadlock Prevention System
Patent:
5,889,972 →
Application:
08/823,958 →
Method and Apparatus for I/O Multiplexing of Ram Bus
Patent:
5,761,129 →
Application:
08/824,202 →
Integrated Circuit Design for Single Ended Receiver Margin Tracking
Patent:
5,831,472 →
Application:
08/829,051 →
Design Verification System Using Expect Buffers
Patent:
5,937,182 →
Application:
08/829,316 →
Reduced-Quality Resolution Digtial Video Encoder/Decoder
Patent:
5,870,144 →
Application:
08/829,463 →
Method and Apparatus for Network Interface Fetching Initial and Data Burst Blocks and Segmenting Blocks and Scheduling Blocks Compatible for Transmission Over Multiple Virtual Circuits
Patent:
5,930,525 →
Application:
08/846,355 →
Methods and Apparatuses for Scheduling Atm Cells
Patent:
5,940,397 →
Application:
08/846,706 →
Programmable Reassembly of Data Received in an Atm Network
Patent:
6,097,734 →
Application:
08/846,707 →
Improved Hardware Control Block Delivery Queues for Host Adapters and Other Devices with Onboard Processors
Patent:
6,012,107 →
Application:
08/862,143 →
Host Adapter Integrated Circuit Having Autoaccess Pause
Patent:
5,960,180 →
Application:
08/869,665 →
System for Aligning Control Words for Identifying Boundaries of Headerless Data Sectors Using Automatic Incrementing and Discarding of Data Frame Numbers
Patent:
6,000,018 →
Application:
08/877,115 →
Hot-Switchable Scsi Controller Having Output Drivers with Quick Turn-On
Patent:
5,919,253 →
Application:
08/882,198 →
Scsi Controller Having Output Driver with Slew Rate Control
Patent:
5,887,150 →
Application:
08/882,199 →
Method and Apparatus for Controlling Clock Skew in an Integrated Circuit
Patent:
5,828,870 →
Application:
08/884,863 →
Object Oriented Simulation Modeling
Patent:
5,923,867 →
Application:
08/903,803 →
High Speed Phase Lock Loop Having High Precision Charge Pump with Error Cancellation
Patent:
5,945,855 →
Application:
08/920,524 →
High Speed Phase Lock Loop Having Constant Bandwidth
Patent:
5,933,037 →
Application:
08/924,009 →
Ghz Transceiver Phase Lock Loop Having Autofrequency Lock Correction
Patent:
5,950,115 →
Application:
08/924,028 →
Multiple Client Memory Arbitration System Capable of Operating Multiple Configuration Types
Patent:
6,023,748 →
Application:
08/928,984 →
Method and Apparatus for Performing Error Correction Code Operations
Patent:
6,041,431 →
Application:
08/933,568 →
Low Voltage Differential Driver with Multiple Drive Strengths
Patent:
5,949,253 →
Application:
08/944,336 →
Low Voltage Differential Dual Receiver
Patent:
6,034,551 →
Application:
08/944,903 →
High Speed Boundary Scan Design
Patent:
6,125,464 →
Application:
08/951,987 →
Method and Apparatus for Automatically Loading Configuration Data on Reset into a Host Adapter Integrated Circuit
Patent:
5,881,281 →
Application:
08/956,224 →
Data Processing System And Virtual Partitioning Method For Creating Logical Multi-Level Units Of Online Storage
Patent:
6,081,879 →
Application:
08/963,899 →
Mechanism for Incremental Backup of on-Line Files
Patent:
6,101,585 →
Application:
08/963,905 →
Method for Reconfiguring Containers Without Shutting Down the System and with Minimal Interruption to on-Line Processing
Patent:
6,032,217 →
Application:
08/964,356 →
Fault to Tolerant Multiple Client Memory Arbitration System Capable of Operating Multiple Configuration Types
Patent:
6,065,102 →
Application:
08/965,718 →
A Timer Based Arbitrations Scheme for a Pci Multi-Function Device
Patent:
6,240,475 →
Application:
09/001,245 →
Method and System for Changing Peripheral Component Interconnect Configuration Registers
Patent:
5,948,076 →
Application:
09/001,615 →
Methods and Apparatus for Communicating Between Networked Peripheral Devices
Patent:
6,101,555 →
Application:
09/005,792 →
Method and Apparatus for Sharing Peripheral Devices Over a Network
Patent:
6,327,613 →
Application:
09/005,799 →
Method and Apparatus for Allocating Exclusive Shared Resource Requests in a Computer System
Patent:
6,105,094 →
Application:
09/013,498 →
Error Correction Method
Patent:
6,457,156 →
Application:
09/015,727 →
Intentionally Mismatched Mirror Process Inverse Current Source
Patent:
5,939,933 →
Application:
09/023,395 →
System for Sharing Peripheral Devices Over a Network and Method for Implementing the Same
Patent:
6,658,459 →
Application:
09/032,364 →
Pipelined Berlekamp-Massey Error Locator Polynomial Generating Apparatus and Method
Patent:
6,092,233 →
Application:
09/046,117 →
An Integrated Circuit Scsi I/O Cell Having Signal Assertion Edge Triggered Timed Glitch Filter That Defines a Strobe Masking Period to Protect the Contents of Data Latches
Patent:
6,055,587 →
Application:
09/049,365 →
Low Capacitance Esd Semiconductor Structure Having a Source Inside a Well and the Bottom Portion of the Drain Inside a Substrate
Patent:
6,114,731 →
Application:
09/049,375 →
Integrated Circuit Scsi Input Receiver Having Precision High Speed Input Buffer with Hysteresis
Patent:
6,084,433 →
Application:
09/055,105 →
Methods and Apparatus for Providing Reduced Bit Rate Digital Video Formats
Patent:
6,233,282 →
Application:
09/062,155 →
Redundant Bus Bridge Systems and Methods Using Separately-Powered Bus Bridges
Patent:
6,154,802 →
Application:
09/062,278 →
Arithmetic Logic Unit and Method for Numerical Computations in Galois Fields
Patent:
6,101,520 →
Application:
09/063,635 →
Multiple Frequency Clock Generation and Synchronization
Patent:
6,064,247 →
Application:
09/072,916 →
Ram Based Error Correction Code Encoder and Syndrome Generator with Programmable Interleaving Degrees
Patent:
6,163,871 →
Application:
09/087,433 →
Device and Method for Extending Error Correction Beyond One Sector Time
Patent:
6,192,499 →
Application:
09/087,731 →
Execution Suspension and Resumption in Multi-Tasking Host Adapters
Patent:
6,253,272 →
Application:
09/088,810 →
System for Register Partitioning in Multi-Tasking Host Adapters by Assigning a Register Set and a Unique Indentifier in Each of a Plurality of Hardware Modules
Patent:
6,243,767 →
Application:
09/089,013 →
Timer Using a Single Counter to Track Multiple Time-Outs
Patent:
6,002,737 →
Application:
09/089,054 →
Communications Interface Adapter for a Computer System Including Posting of System Interrupt Status
Patent:
6,085,278 →
Application:
09/089,068 →
Monitor Port with Selectable Trace Support
Patent:
6,311,303 →
Application:
09/089,278 →
Bus System Expandable by Connection of a Bus Bridge Circuit
Patent:
6,256,689 →
Application:
09/095,908 →
Stacked I/O Bridge Circuit Assemblies Having Flexibly Configurable Connections
Patent:
6,477,593 →
Application:
09/096,033 →
Modular Bus Bridge System Compatible with Multiple Bus Pin Configurations
Patent:
6,098,140 →
Application:
09/096,096 →
A Non-Invasive Bus Master Back-Off Circuit and Method for Systems Having a Plurality of Bus Masters
Patent:
6,112,272 →
Application:
09/096,300 →
High Speed Gain Stage with Dc Offset Cancellation for Servo Demodulator Circuit
Patent:
6,204,980 →
Application:
09/099,666 →
A Scan Cell Including a Propagation Delay and Isolation Element
Patent:
6,412,098 →
Application:
09/107,240 →
Intelligent Backup and Restoring System and Method for Implementing the Same
Patent:
6,205,527 →
Application:
09/110,783 →
Bias Compensator for Differential Transmission Line with Voltage Bias
Patent:
6,124,727 →
Application:
09/113,729 →
Electrostatic Discharge Protection Bus/Die Edge Seal
Patent:
6,078,068 →
Application:
09/116,434 →
One-Piece Multiple-Compartment Shipping and Display Box
Patent:
6,095,408 →
Application:
09/119,716 →
Data Communications System
Patent:
6,442,196 →
Application:
09/127,647 →
Fast-Scan-Flop and Integrated Circuit Device Incorporating the Same
Patent:
6,289,477 →
Application:
09/136,071 →
Parallel Chien Search Circuit
Patent:
6,192,497 →
Application:
09/141,871 →
Low Power Scan Test Cell and Method for Making the Same
Patent:
6,114,892 →
Application:
09/144,485 →
Boundary-Scan Cells with Improved Timing Characteristics
Patent:
6,266,801 →
Application:
09/153,634 →
Data Fram Write and Read Processes
Patent:
6,449,111 →
Application:
09/153,788 →
Modular Bus Bridge
Patent:
6,263,391 →
Application:
09/160,123 →
Automated Test Vector Generation and Verification
Patent:
6,304,837 →
Application:
09/160,553 →
Multi-Processor Bus Protocol System
Patent:
6,449,289 →
Application:
09/169,444 →
Disk Drive Testing
Patent:
6,282,501 →
Application:
09/175,586 →
Format Calculator for Headerless Hard Disk with Embedded Servo Wedges
Patent:
6,144,514 →
Application:
09/177,670 →
Pci Bridge for Optimized Command Delivery
Patent:
6,247,086 →
Application:
09/190,465 →
Apparatus and Method for Generating Interleave Erasure Locations from Thermal Asperity Erasure Pointers
Delay Data Block Release System in a Disk Drive
Patent:
6,256,685 →
Application:
09/197,715 →
Automated Scan Chain Sizing Using Synopsys
Patent:
6,212,656 →
Application:
09/208,594 →
Method and Apparatus for Synchronizing a Decoder Circuit with a Phase-Encoded Data Signal in a Data Storage Device
Patent:
6,167,526 →
Application:
09/222,078 →
Method and Apparatus for Accurately Aligning a Series of Detection Windows with a Synchronization Pattern in a Data Storage Device
Patent:
6,298,101 →
Application:
09/222,509 →
Automated Alternating Current Characterization Testing
Patent:
6,360,353 →
Application:
09/236,957 →
Method and Apparatus for Generating Addresses
Patent:
6,111,986 →
Application:
09/238,106 →
At-Speed Computer Model Testing Methods
Patent:
6,327,556 →
Application:
09/238,387 →
High Speed Raid Cache Controller Using Accelerated Graphics Port
Patent:
6,249,831 →
Application:
09/239,628 →
Drive Preparation Methods for Intelligent Backup Systems
Patent:
6,289,426 →
Application:
09/256,601 →
Method of Generating a Database for Use in an Intelligent Backup and Restoring System
Patent:
6,684,229 →
Application:
09/256,676 →
Method of Finding Application Components in an Intelligent Backup and Restoring System
Patent:
6,934,722 →
Application:
09/256,680 →
Method and Apparatus for Backing Up a Disk Drive Upon a System Failure
Patent:
6,385,707 →
Application:
09/256,681 →
Automated Drive Repair Systems and Methods
Patent:
6,374,366 →
Application:
09/256,682 →
Method for Generating a Footprint Image File for an Intelligent Backup and Restoring System
Patent:
6,374,363 →
Application:
09/256,686 →
Method for Managing Primary and Secondary Storage Device in an Intelligent Backup and Restoring System
Patent:
6,532,535 →
Application:
09/256,687 →
Method and Device for Performing Error Correction on Ecc Data Sectors
Patent:
6,662,334 →
Application:
09/258,246 →
Method and System for Transporting Audio/Video Data Over a Serial Bus
Patent:
6,532,232 →
Application:
09/259,481 →
Low Voltage Differential Driver with Multiple Drive Strengths
Patent:
6,222,388 →
Application:
09/270,947 →
Data Channel Architecture for Parallel Scsi Host Adapters
Patent:
6,408,354 →
Application:
09/275,652 →
Method and Apparatus for Partitioning and Formatting a Storage Media Without Rebooting by Creating a Logical Device Control Block (Dcb) On-The-Fly
Patent:
6,526,493 →
Application:
09/281,596 →
Pci Delayed Transaction Time Out Counter and Associated Methods
Patent:
6,473,826 →
Application:
09/295,051 →
Host Adapter Integrated Circuit Having Autoaccess Pause
Patent:
6,202,117 →
Application:
09/302,017 →
Hard Disk Bootstrap Redirection
Patent:
6,415,382 →
Application:
09/302,921 →
Scan Flop Circuitry and Methods for Making the Same
Patent:
6,393,592 →
Application:
09/316,492 →
Gated Clock Flip-Flops
Patent:
6,275,081 →
Application:
09/325,013 →
Format Calculator for Headerless Hard Disk with Embedded Servo Wedges
Patent:
6,049,436 →
Application:
09/339,069 →
Scsi Bus Free Phase Management Structure and Method of Operation for Parallel Scsi Host Adapter Integrated Circuits
Patent:
6,477,601 →
Application:
09/343,323 →
Structure and Method for Automatic Configuration for Scsi Synchronous Data Transfers
Patent:
6,457,090 →
Application:
09/343,492 →
Nfet/Pfet Ram Precharge Circuitry to Minimize Read Sense Amp Operational Range
Patent:
6,108,256 →
Application:
09/395,922 →
Bridge Device for Transferring Data Using Master-Specific Prefetch Sizes
Patent:
6,636,927 →
Application:
09/405,345 →
Circuit and Method for Synchronized Data Banking
Patent:
6,282,149 →
Application:
09/448,027 →
System and Method for Disk Control with Snapshot Feature Including Read-Write Snapshot Half
Patent:
6,341,341 →
Application:
09/465,354 →
System for on-Line Disk System Configuration
Patent:
6,275,892 →
Application:
09/474,204 →
Low Voltage Differential Dual Receiver
Patent:
6,307,401 →
Application:
09/479,464 →
Ethernet Storage Protocol Networks
Patent:
6,738,821 →
Application:
09/490,629 →
Methods for Implementing an Ethernet Storage Protocol in Computer Networks
Patent:
7,031,904 →
Application:
09/490,630 →
Integrated circuit SCSI input receiver having precision high speed input buffer with hysteresis
Patent:
6,144,223 →
Application:
09/525,873 →
Methods and Apparatus for Implementing a Device Side Advanced Serial Protocol
Patent:
6,675,243 →
Application:
09/526,028 →
Host and Device Serial Communication Protocols and Communication Packet Formats
Patent:
6,609,167 →
Application:
09/526,030 →
Methods and Apparatus for Implementing a Host Side Advanced Serial Protocol
Patent:
6,636,922 →
Application:
09/526,293 →
Dual mode phase and frequency detector
Patent:
6,285,219 →
Application:
09/539,480 →
Key-Based Collision Detection Algorithm for Multi-Initiator Domain Validation
Patent:
7,072,988 →
Application:
09/540,163 →
Package for a Software Application
Patent:
6,401,919 →
Application:
09/545,148 →
Methods for Predicting Reliability of Semiconductor Devices Using Voltage Stressing
Patent:
6,414,508 →
Application:
09/557,747 →
Dynamic File System Configurations
Patent:
6,714,949 →
Application:
09/558,318 →
One-piece multiple-compartment shipping and display box
Patent:
6,237,842 →
Application:
09/559,209 →
Method for Protecting Data of a Computer System
Patent:
6,901,493 →
Application:
09/566,910 →
Methods for Selecting a Boot Partition and Hiding a Non-Selected Partition
Patent:
6,430,663 →
Application:
09/568,087 →
Programmable reassembly of data received in an atm network
Patent:
6,327,271 →
Application:
09/568,561 →
Programmable Generic Read Channel Control Device
Patent:
6,529,973 →
Application:
09/576,705 →
Multi-Layer Printed Circuit Board with Dual Impedance Section
Patent:
6,365,839 →
Application:
09/587,307 →
Programmable analog-to-digital converter with bit conversion optimization
Patent:
6,329,938 →
Application:
09/595,437 →
Hard Drive with Format Calculator for Generating Sector Numbers on Track
Patent:
6,487,029 →
Application:
09/602,563 →
Message Signaled Interrupt Generating Device and Method
Patent:
6,629,179 →
Application:
09/630,341 →
Methods for Addressing Extended Number of Peripheral Devices Over Peripheral Bus
Patent:
6,708,242 →
Application:
09/636,038 →
Network Stack Layer Interface
Patent:
6,651,117 →
Application:
09/680,142 →
Dual Mode Clock Alignment and Distribution Device
Patent:
6,687,322 →
Application:
09/680,918 →
Intelligent Backup and Restoring System and Method for Implementing the Same
Patent:
6,477,629 →
Application:
09/715,589 →
Congestion Control for Internet Protocol Storage
Method and System for Data Streaming During the Data in Phase of the Packetized Scsi Protocol
Patent:
6,745,260 →
Application:
09/745,037 →
Method and Structure for Supporting Data Streaming by a Scsi Target During the Data in Phase of the Packetized Scsi Protocol
Patent:
6,728,815 →
Application:
09/745,105 →
Device Discovery Methods and Systems Implementing the Same
Patent:
7,225,243 →
Application:
09/809,602 →
Method and Structure for Automatic Scsi Command Delivery Using the Packetized Scsi Protocol
Patent:
6,883,042 →
Application:
09/842,750 →
Low Voltage Differential Dual Receiver
Compact Disc Package System and Methods for Packaging the Same
Patent:
6,681,928 →
Application:
09/972,600 →
Method and Apparatus for Sharing Peripheral Devices Over a Network
Method and Apparatus for Operating a Computer in a Secure Mode
Patent:
7,043,643 →
Application:
10/006,049 →
Method and Apparatus for a Secure Computing Environment
Patent:
7,260,726 →
Application:
10/006,308 →
Method for Processing Data Packet Headers
Patent:
6,996,105 →
Application:
10/029,186 →
Method and Apparatus for Merging Contiguous Like Commands
Patent:
6,931,501 →
Application:
10/045,128 →
Systems and Methods for Synchronizing a Signal Across Multiple Clock Domains in an Integrated Circuit
Patent:
7,007,186 →
Application:
10/074,952 →
Unified Services Entitlement Architecture
Patent:
7,502,459 →
Application:
10/086,270 →
Apparatuses and Methods for Modeling Shared Bus Systems
Patent:
7,110,928 →
Application:
10/090,353 →
System and Method of Software/Firmware Uploading and Upgrading for Peripheral Devices
Patent:
7,010,624 →
Application:
10/114,169 →
System and Method for Determining Integrated Circuit Logic Speed
Patent:
6,966,022 →
Application:
10/116,922 →
Precomp Cutback Differential Driver
Patent:
6,664,811 →
Application:
10/121,485 →
Method and Apparatus for Developing Multiple Test Cases from a Base Test Case
Patent:
6,892,154 →
Application:
10/140,236 →
System and Method for an Interface Invariant Test Case
Patent:
6,732,060 →
Application:
10/140,307 →
Methods for Congestion Mitigation in Infiniband
Patent:
7,000,025 →
Application:
10/141,147 →
Modular Peripheral Device Hub
Patent:
6,983,341 →
Application:
10/153,462 →
Method and Apparatus for Increasing the Performance of Communications Between a Host Processor and a Sata or Ata Device
Patent:
7,130,932 →
Application:
10/191,958 →
Apparatus and Method for Programmable Dual Stage Digital Filter
Patent:
7,206,798 →
Application:
10/209,494 →
Method and Apparatus for a Programmable Deskew Circuit
Patent:
6,915,462 →
Application:
10/209,552 →
Method to Transmit Bits of Data Over a Bus
Patent:
7,272,194 →
Application:
10/215,069 →
Methods and Apparatus to Correct Duty Cycle
Patent:
6,981,185 →
Application:
10/215,919 →
Method and Apparatus for Data Bit Align
Patent:
7,324,421 →
Application:
10/218,313 →
Methods and Apparatus for Modeling and Verifying a Set of Pci Bus Transactions
Patent:
6,895,367 →
Application:
10/300,452 →
Systems and Methods Optimizing Data Transfer Throughput of a System on Chip
Bootable Cd for Transferring Files Independently of Computer Operating Systems
Patent:
7,024,493 →
Application:
10/640,931 →
Method and Apparatus for Accelerating Test Case Development
Patent:
7,231,616 →
Application:
10/645,729 →
Integrated Circuit Verification Scheme
Patent:
7,137,087 →
Application:
10/645,789 →
Method and Apparatus for a Pipeline Architecture
Method and Apparatus for Aligning Operands for a Processor
Centralized Console Api Testing Architecture
Patent:
7,016,800 →
Application:
10/738,312 →
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Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 18, 2013
From: RPX CORPORATION
To: HTC CORPORATION
Reel/Frame 030825/0400 →
Merger
Aug 6, 2013
From: FUTURE DOMAIN CORPORATION
To: POWER I/O, INC.
Reel/Frame 030947/0323 →
Merger
Aug 6, 2013
From: POWER I/O, INC.
To: ADAPTEC, INC.
Reel/Frame 030966/0792 →
Change of Name
Aug 6, 2013
From: ADAPTEC, INC.
To: ADPT CORPORATION
Reel/Frame 030966/0867 →
Assignment of Assignor's Interest
Aug 8, 2014
From: HTC CORPORATION
To: 8631654 CANADA INC.
Reel/Frame 033493/0466 →
Merger and Change of Name
Jun 28, 2017
From: 8631654 CANADA INC.; QUARTERHILL INC.
To: QUARTERHILL INC.
Reel/Frame 043027/0098 →
Assignment of Assignor's Interest
Jul 21, 2017
From: QUARTERHILL INC.
To: WI-LAN INC.
Reel/Frame 043285/0115 →