IP Library Granted Patent US 7,231,616
Granted Patent B1
US 7,231,616 · App. 10/645,729 · Granted Jun 12, 2007

Method and apparatus for accelerating test case development

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Quick Facts
Patent No.
US 7,231,616
App. No.
10/645,729
Granted
Jun 12, 2007
Kind
B1
Abstract

A system configured to minimize validation time associated with an integrated circuit design is provided. The system includes a client and a server. The client is configured to identify a test case for simulation with the integrated circuit design. The client is further configured to generate a verified file from the test case. The server is in communication with the client. The server is configured to maintain an initialized state. The server, when in the initialized state, is configured to receive the verified file from the client for execution, wherein after execution of the verified file, the server is enabled to communicate results to the client and the server resets to the initialized state. A method for submitting a test case for simulation of an integrated circuit design and a computer readable medium are also provided.

Claims (42)

1. A method for submitting a test case for simulation of an integrated circuit design, comprising:

identifying a test case associated with a client;

verifying the test case at the client;

submitting the test case to a pre-initialized simulation server from the client;

associating text file based tasks of the test case to hardware description language (HDL) based tasks;

executing the HDL based tasks on a model of an integrated circuit design associated with the simulation server;

communicating results from the test case execution to the client; and

executing a reset and initialization sequence at the pre-initialized simulation server to maintain the pre-initialized simulation server in an initialized state for a next test case.

2. The method of claim 1 , wherein the method operation of verifying the test case at the client includes,

checking a syntax and a format of tasks defining the test case.

3. The method of claim 1 , wherein the results are formatted as a results.log file.

4. The method of claim 1 , further comprising:

providing a queue associated with the pre-initialized simulation server, the queue configured to store the test case.

5. The method of claim 1 , wherein the method operation of communicating results from the test case execution to the client includes,

uninitializing the simulation server.

6. The method of claim 1 , wherein the method operation of executing the test case on the pre-initialized simulation server includes,

translating each text based task associated with the verified test case to a compiled hardware description language (HDL) task.

7. The method of claim 6 , wherein the compiled HDL task is stored on a storage media associated with the simulation server.

8. A computer readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to perform a method for minimizing simulation time overhead associated with the validation of an integrated circuit design, the method comprising:

executing a reset and initialization sequence at a server to maintain the server in an initialized state;

receiving a verified test case from a client in communication with the server;

associating text-file based tasks of the test case to hardware description language (HDL) based tasks;

executing the HDL based tasks on a model of an integrated circuit design associated with the server recording results associated with execution of the test case;

communicating the results to the client; and

resetting the server to maintain the initialized state for receiving a next test case.

9. The computer readable medium of claim 8 , wherein executing the test case and recording results associated with execution of the test case includes,

translating each of a text-based task associated with the verified test case to a compiled hardware description language (HDL) task.

10. The computer readable medium of claim 8 , wherein communicating the results to the client includes,

uninitializing the server.

11. The computer readable medium of claim 8 , wherein communicating the results to the client includes,

generating a results.log file.

12. A system configured to minimize validation time associated with an integrated circuit design, comprising:

a client, the client configured to identify a test case for simulation with the integrated circuit design, the client further configured to generate a verified file from the test case, wherein the verified file includes text based tasks associated with hardware description language (HDL) based tasks;

a server in communication with the client; the server configured to maintain an initialized state, the server when in the initialized state configured to receive the HDL based tasks of the verified file from the client for execution, wherein after execution of the HDL based tasks of the verified file on a model of an integrated circuit design associated with the server, the server is enabled to communicate results to the client and the server resets to the initialized state.

13. The system of claim 12 , further comprising:

a storage medium in communication with the server, the storage medium configured to store compiled hardware description language based tasks corresponding to text based tasks associated with the verified file.

14. The system of claim 12 , further comprising:

a network providing a communication pathway between the server and the client.

15. The system of claim 12 , wherein the verified filed includes a sequence of text-based tasks.

16. The system of claim 12 , wherein the results are contained within a log-based file.

17. The system of claim 12 , wherein the server further includes a queue, the queue configured to store a plurality of verified files.

18. The system of claim 12 , wherein both the client and the server are general purpose computers.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
MERGER AND CHANGE OF NAME Recorded May 30, 2018
From: ADPT CORPORATION; ADAPTEC, INC.
To: ADPT CORPORATION
Reel/Frame 046268/0592 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2012
From: HUPPER ISLAND LLC
To: RPX CORPORATION
Reel/Frame 028142/0922 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2011
From: ADPT CORPORATION
To: HUPPER ISLAND LLC
Reel/Frame 026459/0871 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2004
From: THANGAVELU, SIVAM
To: ADAPTEC, INC.
Reel/Frame 014903/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2003
From: MOHANTY, PURNA; JAMBHEKAR, VIVEK
To: ADAPTEC, INC.
Reel/Frame 014411/0099 →