Method and system for sharing a receive buffer RAM with a single DMA engine among multiple context engines
View Patent ↗A method for sharing a buffer among multiple context engines, is provided. The method includes loading a memory element with a first data sequence. The method further includes loading a corresponding first context information to one of the multiple context engines. Subsequently, a direct memory access engine is loaded with the first data sequence dictated by the first context information. Then, the first data sequence is processed. While the first data sequence is being processed, the method includes loading the context engine with a next context information for a next data sequence contemporaneously with the processing of the first data sequence.
1. A method to share a buffer among multiple context engines, comprising:
loading the buffer with a first data sequence;
loading a first context information associated with the first data sequence to one of the multiple context engines;
loading a direct memory access engine that is shared with the multiple context engines with the first data sequence as directed by the first context information;
processing the first data sequence through the direct memory access engine; and
while processing the first data sequence, loading the one of the multiple context engines with a next context information for a next data sequence of the buffer contemporaneously with the processing of the first data sequence.
2. The method of claim 1 , further comprising:
retrieving the first data sequence after the processing; and
storing the first data sequence in a common resource location.
3. A system for efficiently transferring a data sequence, comprising:
a storage element storing the data sequence;
a context engine configured to store context information for the data sequence;
a status machine configured to determine a status of the transferring of the data sequence; and
a direct memory access (DMA) engine in communication with the storage element to receive the data sequence from the storage element as directed by the context information.
4. The system of claim 3 , further comprising:
a context memory that stores context information for the data sequence.
5. The system of claim 4 wherein the context information includes, an address to which the data sequence is written to or pulled from.
6. The system of claim 3 , wherein the storage element is a buffer.
7. The system of claim 4 , wherein the status machine is configured to signal the context to load the context information for a next data sequence to be loaded to the DMA engine.
8. A system that maximizes data transmission by switching between two context engines, comprising:
a buffer configured to receive a data sequence;
a direct memory access engine in communication with the buffer;
at least two context engines configured to direct transfer of the data sequence between the buffer and the direct memory access engine; and
an arbiter in communication with the context engines, wherein the arbiter is configured to arbitrate between the at least two context engines to select the data sequence corresponding to one of the context engines to be loaded to the direct memory access engine.
9. The system of claim 8 , wherein the at least two context engines hold context information for different contexts.
10. The system of claim 9 , wherein the context information includes, an address in a memory to which the data sequence is to be forwarded.
11. The system of claim 10 , wherein the context information include, a count wherein the count include, the number of bits in the data sequence.
12. The system of claim 8 , wherein the arbiter is configured to select the data sequence based on the time the context is loaded into the context engine.
13. The system of claim 8 , wherein the arbiter is configured to select the data sequence based on the time the data sequence loaded into the buffer.