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Patent Assignment
Reel/Frame 031133/0030

Assignment of Assignor's Interest

Recorded: 2013-09-02 Pages: 2
Assignors
LEE, CHIA-YING
Executed: 2013-08-12
SHIEH, JYU-HORNG
Executed: 2013-08-12
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77 R.O.C., TAIWAN
Covered Property (1)
Method of Fine Line Space Resolution Lithography for Integrated Circuit Features Using Double Patterning Technology
Patent: 9,204,538 →
Application: 13/968,804 →
Publication: US 2015/0047891