IP Library Assignment 031441/0146
Patent Assignment
Reel/Frame 031441/0146

Assignment of Assignor's Interest

Recorded: 2013-09-26 Pages: 3
Assignors
HARADA, HIROFUMI
Executed: 2013-09-05
HASHITANI, MASAYUKI
Executed: 2013-09-05
Assignee
SEIKO INSTRUMENTS INC.
8, NAKASE 1-CHOME, MIHAMA-KU, CHIBA-SHI, CHIBA, 261-8507, JAPAN
Covered Property (1)
Semiconductor integrated circuit device comprising an enhancement type NMOS having a positive threshold voltage and an depression type NMOS having a negative threshold voltage, wherein a P-type impurity layer provided under the N-type channel impurity region.
Application: 14/033,842 →
Publication: US 2014/0084378
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 10, 2016
From: SEIKO INSTRUMENTS INC.
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 038058/0892 →