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App. No. 14/033,842 · Confirmation No. 3141

Semiconductor integrated circuit device comprising an enhancement type NMOS having a positive threshold voltage and an depression type NMOS having a negative threshold voltage, wherein a P-type impurity layer provided under the N-type channel impurity region.

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Quick Facts
App. No.
14/033,842
Filed
2013-09-23
Pub. No.
US20140084378A1
Art Unit
2823