IP Library Assignment 032248/0269
Patent Assignment
Reel/Frame 032248/0269

Assignment of Assignor's Interest

Recorded: 2014-02-19 Pages: 6
Assignors
GOVINDARAJU, SRIDHAR
Executed: 2013-12-20
PRINCE, MATTHEW J.
Executed: 2013-12-20
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Techniques and Configurations to Reduce Transistor Gate Short Defects
Patent: 9,281,401 →
Application: 14/137,909 →
Publication: US 2015/0179785