Patent Assignment
Reel/Frame 032489/0556
Assignment of Assignor's Interest
Recorded: 2014-03-20
Pages: 8
Assignors
JENSEN, MARK
Executed: 2014-03-07
GOODRICH, ANDREW
Executed: 2014-03-07
FOURON, VALERY
Executed: 2014-03-10
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
Design Synthesis of Clock Gated Circuit