Patent Assignment
Reel/Frame 032770/0477
Assignment of Assignor's Interest
Recorded: 2014-04-28
Pages: 8
Assignors
KODAMA, CHIKAAKI
Executed: 2014-01-14
NAKAYAMA, KOICHI
Executed: 2014-01-14
KOTANI, TOSHIYA
Executed: 2014-01-14
NOJIMA, SHIGEKI
Executed: 2014-01-14
NAKAJIMA, FUMIHARU
Executed: 2014-01-14
ICHIKAWA, HIROTAKA
Executed: 2014-01-14
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO, 105-8001, JAPAN
Covered Property
(1)
Design Method of Wiring Layout, Semiconductor Device, Program for Supporting Design of Wiring Layout, and Method for Manufacturing Semiconductor Device
Application:
14/133,278 →
Publication:
US 2014/0183702