IP Library › Assignment 034062/0143
Patent Assignment
Reel/Frame 034062/0143

Assignment of Assignor's Interest

Recorded: 2014-10-29 Pages: 3
Assignors
SHIBASAKI, TAKAYUKI
Executed: 2014-10-03
TSUNODA, YUKITO
Executed: 2014-10-03
Assignee
FUJITSU LIMITED
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN
Covered Property (1)
Multi-Lane Re-Timer Circuit and Multi-Lane Reception System
Patent: 9,287,883 →
Application: 14/525,957 →
Publication: US 2015/0200768