Patent Assignment
Reel/Frame 034117/0018
Assignment of Assignor's Interest
Recorded: 2014-11-06
Pages: 5
Assignors
IWANAGA, SHUJI
Executed: 2014-10-30
NISHIYAMA, TADASHI
Executed: 2014-10-30
TOMITA, HIROSHI
Executed: 2014-10-30
HASEGAWA, IZUMI
Executed: 2014-10-30
Assignee
TOKYO ELECTRON LIMITED
3-1, AKASAKA 5-CHOME, MINATO-KU, TOKYO, 107-6325, JAPAN
Covered Property
(1)
Defect Analyzing Apparatus, Substrate Processing System, Defect Analyzing Method and Computer-Readable Storage Medium