IP Library Assignment 034130/0244
Patent Assignment
Reel/Frame 034130/0244

Assignment of Assignor's Interest

Recorded: 2014-11-07 Pages: 4
Assignors
SHIH, YU-LIN
Executed: 2014-11-05
LEE, CHIH-CHENG
Executed: 2014-11-05
Assignee
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
26 CHIN 3RD ROAD, NANTZE EXPORT PROCESSING ZONE, KAOHSIUNG, TAIWAN
Covered Property (1)
Semiconductor Package with Reduced via Hole Width and Reduced Pad Patch and Manufacturing Method Thereof
Patent: 9,721,799 →
Application: 14/536,253 →
Publication: US 2016/0133537