IP Library › Assignment 034736/0635
Patent Assignment
Reel/Frame 034736/0635

Assignment of Assignor's Interest

Recorded: 2015-01-16 Pages: 4
Assignors
KODAMA, CHIKAAKI
Executed: 2014-12-18
NAKAYAMA, KOICHI
Executed: 2014-12-18
KOTANI, TOSHIYA
Executed: 2014-12-19
NOJIMA, SHIGEKI
Executed: 2014-12-19
NAKAJIMA, FUMIHARU
Executed: 2014-12-18
ICHIKAWA, HIROTAKA
Executed: 2014-12-25
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO, 105-8001, JAPAN
Covered Property (1)
Design Method of Wiring Layout, Semiconductor Device, Program for Supporting Design of Wiring Layout, and Method for Manufacturing Semiconductor Device
Patent: 9,953,126 →
Application: 14/506,436 →
Publication: US 2015/0021782
Related Assignments (4)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
Change of Name and Address Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
Merger Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
Change of Name and Address Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →