Patent Assignment
Reel/Frame 034778/0153
Assignment of Assignor's Interest
Recorded: 2015-01-21
Pages: 60
Assignor
LSI CORPORATION
Executed: 2014-09-02
Assignee
SEAGATE TECHNOLOGY LLC
10200 S. DE ANZA BLVD., CUPERTINO, CALIFORNIA, 95014
Covered Properties
(25)
Managing a Dynamically Variable Cache Space
Application:
61/614,548 →
Fractional Redundant Array of Silicon Independent Elements
Application:
61/682,561 →
Log-Likelihood Ratio (LLR) Dampening in Low-Density Parity-Check (LDPC) Decoders
Application:
61/729,178 →
Policy for flash memory read operations
Application:
61/735,908 →
Error correction code rate management for flash memory
Application:
61/735,917 →
Flash memory read error recovery policy with soft-decision LDPC decoder
Application:
61/735,923 →
Adaptive Architecture in a Channel Detector for Nand Flash Channels
Application:
61/766,853 →
Self Recovery in a Solid State Drive
Application:
61/773,337 →
Partial R-Block Recycling
Application:
61/773,437 →
Retention Detection and/or Channel Tracking Policy in a Flash Memory Based Storage System
Application:
61/777,048 →
Nonvolatile Memory Data Recovery After Power Failure
Application:
61/781,744 →
I/O Device with Multi-Reducible-Unit Mapping
Application:
61/782,089 →
Storage Device Assisted Data De-Duplication
Application:
61/782,122 →
Method and Apparatus for Generation of Soft Decision Error Correction Code Information
Application:
61/782,837 →
Trim Mechanism Using Multi-Level Mapping in a Solid-State Media
Application:
61/783,555 →
Device Sleep Partitioning and Keys
Application:
61/789,337 →
Unified Message-Based Communications
Application:
61/789,574 →
Dynamic Log Likelihood Ratio Quantization for Solid State Drive Controllers
Application:
61/804,265 →
Method of Optimizing Solid State Drive Soft Retry Voltages
Application:
61/804,853 →
Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders
Application:
61/805,195 →
Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder
Application:
61/805,270 →
Flash Translation Layer with Lower Write Amplification
Application:
61/817,441 →
Systems and Methods for Inter-cell Interference Mitigation in a Flash Memory
Application:
61/826,464 →
Protection of Data in Memory
Application:
61/828,425 →
Systems and Methods for Enhanced Data Recovery in a Solid State Memory System
Application:
61/883,123 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 23, 2013
From: QUINN, ROBERT F.
To: LSI CORPORATION
Reel/Frame 030268/0781 →
Assignment of Assignor's Interest
Jul 11, 2013
From: COHEN, EARL T.
To: LSI CORPORATION
Reel/Frame 030776/0366 →
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Termination and Release of Security Interest in Certain Patents Included in Security Interest Previously Recorded at Reel/Frame (032856/0031)
Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →