Patent Assignment
Reel/Frame 034177/0257
Termination and Release of Security Interest in Certain Patents Included in Security Interest Previously Recorded at Reel/Frame (032856/0031)
Recorded: 2014-11-06
Pages: 57
Assignor
DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Executed: 2014-09-02
Assignees
LSI CORPORATION
1310-1320 RIDDER PARK DRIVE, SAN JOSE, CALIFORNIA, 95131
AGERE SYSTEMS LLC
1110 AMERICAN PARKWAY NE, ALLENTOWN, PENNSYLVANIA, 18109
Covered Properties
(210)
Self-Journaling and Hierarchical Consistency for Non-Volatile Storage
PCT:
PCT/US2012/058583 ↗
System, Method, and Computer Program Product for Delaying an Operation That Reduces a Lifetime of Memory
System, Method, and Computer Program Product for Reducing Memory Write Operations Using Difference Information
Multi-Memory Device System and Method for Managing a Lifetime Thereof
Memory Lifetime Gauging System, Method and Computer Program Product
System, Method, and Computer Program Product for Providing Data Redundancy in a Plurality of Storage Devices
System and Method for Providing Data Redundancy After Reducing Memory Writes
System, Method, and Computer Program Product for Increasing a Lifetime of a Plurality of Blocks of Memory
System, Method and a Computer Program Product for Writing Data to Different Storage Devices Based on Write Frequency
System, Method, and Computer Program Product for Increasing Spare Space in Memory to Extend a Lifetime of the Memory
System, Method, and Computer Program Product for Providing an Extended Capability to a System
Application:
12/173,631 →
Publication:
US 2010/0017588
System, Method, and Computer Program Product for Transparent Communication Between a Storage Device and an Application
Application:
12/173,643 →
Publication:
US 2010/0017807
Techniques for Interfacing Computing Device Hardware of a Computing Device and an Operating System Utilizing a Virtualization Layer
Application:
12/173,654 →
Publication:
US 2010/0017566
System, Method, and Computer Program Product for Converting Data in a Binary Representation to a Non-Power of Two Representation
Application:
12/207,379 →
Publication:
US 2010/0064093
System, Method, and Computer Program Product for Rendering at Least a Portion of Data Useless in Immediate Response to a Delete Command
Application:
12/330,183 →
Publication:
US 2010/0146236
System, Method, and Computer Program Product for Converting Logical Block Address De-Allocation Information in a First Format to a Second Format
System, Method, and Computer Program Product for Sending Logical Block Address De-Allocation Status Information
System, Method, and Computer Program Product for Hardening Data Stored on a Solid State Disk
Application:
12/413,329 →
Publication:
US 2010/0250830
System, Method, and Computer Program Product for Ordering a Plurality of Write Commands Associated with a Storage Device
Application:
12/497,327 →
Publication:
US 2011/0004718
System, Method, and Computer Program Product for Interfacing One or More Storage Devices with a Plurality of Bridge Chips
System, Method, and Computer Program Product for Inserting a Gap in Information Sent from a Drive to a Host Device
System, Method, and Computer Program Product for Reducing a Rate of Data Transfer to at Least a Portion of Memory
Techniques for Maintaining a Connection Between an Initiator and a Drive
Application:
12/508,259 →
Publication:
US 2011/0022765
System, Method, and Computer Program Product for Sending Failure Information from a Serial Ata (Sata) Solid State Drive (Ssd) to a Host Device
Techniques for Multi-Memory Device Lifetime Management
Techniques for Prolonging a Lifetime of Memory by Controlling Operations That Affect the Lifetime of the Memory
Techniques for Writing Data to Different Portions of Storage Devices Based on Write Frequency
Techniques for Reducing Memory Write Operations Using Coalescing Memory Buffers and Difference Information
Reducing Writes, and Estimating and Displaying Estimated Remaining Lifetime of Non-Volatile Memories
Techiniques for Increasing a Lifetime of Blocks of Memory
Techniques for Providing Data Redundancy After Reducing Memory Writes
Accessing Compressed Data of Varying-Sized Quanta in Non-Volatile Memory
Patent:
9,396,104 →
Application:
13/053,175 →
Encryption Key Destruction For Secure Data Erasure
Storage System Logical Block Address De-Allocation Management
Cross-Decoding for Non-Volatile Storage
Sending Failure Information from a Solid State Drive (Ssd) to a Host Device
Ordering a Plurality of Write Commands Associated with a Storage Device
System, Method, and Computer Program Product for Inserting a Gap in Information Sent from a Drive to a Host Device
Solid-State Disk Manufacturing Self Test
Zero-One Balance Management in a Solid-State Disk Controller
Fast Tracking for Flash Channels
Application:
13/533,130 →
Publication:
US 2013/0343131
Flash Memory Read Error Rate Reduction
Application:
13/555,444 →
Publication:
US 2014/0026003
Mixed Granularity Higher-Level Redundancy for Non-Volatile Memory
Single-Read Based Soft-Decision Decoding of Non-Volatile Memory
Soft-Decision Compensation for Flash Channel Variation
Techniques for Increasing a Lifetime of Blocks of Memory
LDPC Erasure Decoding for Flash Memories
Memory Device Having Collaborative Filtering to Reduce Noise
Threshold Optimization for Flash Memory
Flash Memory Read Scrub and Channel Tracking
Lookup Engine with Pipelined Access, Speculative Add and Lock-in-Hit Function
Measuring Cell Damage for Wear Leveling in a Non-Volatile Memory
Flash Channel Parameter Management with Read Scrub
Optimized Bitstream Encoding for Compression
Optimizing Compression Engine Throughput via Run Pre-Processing
Accelerated Soft Read for Multi-Level Cell Nonvolatile Memories
Scalable Data Structures for Control and Management of Non-Volatile Storage
Fractional Redundant Array of Silicon Independent Elements
Scalable Storage Protection
Scalable Storage Devices
Method to Apply Fine Grain Wear Leveling and Garbage Collection
Application:
13/724,905 →
Non-Volatile Memory Program Failure Recovery Via Redundant Arrays
Storage System Data Hardening
Method to Apply Fine Grain Wear Leveling and Garbage Collection
Low-Density Parity-Check Decoder Disparity Preprocessing
Chained, Scalable Storage Devices
Application:
13/765,253 →
Publication:
US 2013/0159622
Physical-To-Logical Address Map to Speed Up a Recycle Operation in a Solid State Drive
Error Correction Code Rate Management for Nonvolatile Memory
Flash Memory Read Error Recovery with Soft-Decision Decode
Policy for Read Operations Addressing on-the-Fly Decoding Failure in Non-Volatile Memory
Techniques for Reducing Memory Write Operations Using Coalescing Memory Buffers and Difference Information
Host Command Based Read Disturb Methodology
Method of Optimizing Solid State Drive Soft Retry Voltages
System, Method, and Computer Program Product for Inserting a Gap in Information Sent from a Drive to a Host Device
Device Sleep Partitioning and Keys
Adaptive Ecc Techniques for Flash Memory Based Data Storage
Application:
13/879,383 →
Publication:
US 2014/0136927
Sending Failure Information from a Solid State Drive (Ssd) to a Host Device
Variable Redundancy in a Solid State Drive
Systems and Methods for Inter-Cell Interference Mitigation in a Flash Memory
I/O Device and Computing Host Interoperation
Application:
13/936,010 →
Publication:
US 2013/0297894
Storage Device Assisted Data De-Duplication
Application:
13/939,345 →
Publication:
US 2014/0281155
Techniques for Providing Data Redundancy After Reducing Memory Writes
Locating Data in Non-Volatile Memory
Techniques for Increasing a Lifetime of Blocks of Memory
Trim Mechanism Using Multi-Level Mapping in a Solid-State Media
Application:
13/963,074 →
Publication:
US 2014/0047210
Techniques For Reducing A Rate Of Data Transfer To At Least A Portion Of Memory
Higher-Level Redundancy Information Computation
Selective Enablement of Operating Modes or Features via Host Transfer Rate Detection
Self-Journaling and Hierarchical Consistency for Non-Volatile Storage
Storage Device Firmware and Manufacturing Software
Application:
13/988,741 →
Publication:
US 2014/0059278
Dynamic Higher-Level Redundancy Mode Management with Independent Silicon Elements
Maintaining Ordering via a Multi-Level Map of a Solid-State Media
Virtual Bands Concentration for Self Encrypting Drives
Systems and Methods for Enhanced Data Recovery in a Solid State Memory System
Flash Memory Read Retry Using Histograms
Patent:
8,953,373 →
Application:
14/052,252 →
Variable-Size Flash Translation Layer
Flash Memory Reference Voltage Detection with Tracking of Cross-Points of Cell Voltage Distributions Using Histograms
Translation Layer Partitioned Between Host and Controller
Generating Soft Decoding Information for Flash Memory Error Correction Using Hard Decision Patterns
Systems and Methods for Latency Based Data Recycling in a Solid State Memory System
Systems and Methods for Soft Data Utilization in a Solid State Memory System
Active Recycling for Solid State Drive
Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell
Reduction or Elimination of a Latency Penalty Associated with Adjusting Read Thresholds for Non-Volatile Memory
Method of Managing Aligned and Unaligned Data Bands in a Self Encrypting Solid State Drive
Tracking and Utilizing Second Level Map Index for Recycling of Solid State Drive Blocks
Flash Channel With Selective Decoder Likelihood Dampening
Eliminating or Reducing Programming Errors When Programming Flash Memory Cells
Bit-Line Defect Detection Using Unsatisfied Parity Code Checks
System, Method, and Computer Program Product for Inserting a Gap in Information Sent from a Drive to a Host Device
Systems and Methods for Soft Decision Generation in a Solid State Memory System
Techniques for Dynamically Determining Allocations and Providing Variable Over-Provisioning for Non-Volatile Storage
Encrypted-Transport Solid-State Disk Controller
Management of Device Firmware Update Effects as Seen by a Host
Techniques For Secure Storage Hijacking Protection
Read Retry For Non-Volatile Memories
Multiple Retry Reads in a Read Channel of a Memory
Decoding with Log Likelihood Ratios Stored in a Controller
Preventing Programming Errors from Occurring When Programming Flash Memory Cells
Storage Address Space to Nvm Address, Span, and Length Mapping/Converting
Management of and Region Selection for Writes to Non-Volatile Memory
Non-Deterministic Encryption
Decoupled Locking Dma Architecture
Retention-Drift-History-Based Non-Volatile Memory Read Threshold Optimization
Systems and Methods for Hard Error Reduction in a Solid State Memory Device
Higher-Level Redundancy Information Computation
System to Control a Width of a Programming Threshold Voltage Distribution Width When Writing Hot-Read Data
Systems and Methods for Last Written Page Handling in a Memory Device
Scalable Storage Devices
Periodically Updating a Log Likelihood Ratio (Llr) Table in a Flash Memory Controller
Lock-Free Communication Storage Request Reordering
Tamper Sensor
Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus
Techniques for Reducing Memory Write Operations Using Coalescing Memory Buffers and Difference Information
Storage System Data Hardening
Storage Device Power Failure Infrastructure
Enhanced Queue Management
I/O Device and Computing Host Interoperation
Techniques for Controlling Recycling of Blocks of Memory
Cross-Decoding for Non-Volatile Storage
Techniques for Providing Data Redundancy After Reducing Memory Writes
Method and apparatus for reducing and distributing writes
Application:
60/860,843 →
Method and system using intra-drive redundancy for reducing cost and improving performance of storage subsystem
Application:
60/873,630 →
Method and apparatus guaranteeing lifetime in pressure of operations reducing lifetime
Application:
60/878,242 →
LDPC Erasure Decoding for Flash Memories
Application:
61/313,681 →
Accessing Compressed Data of Varying-Sized Quanta in Non-Volatile Memory
Application:
61/316,373 →
Scalable Storage Devices
Application:
61/356,443 →
Encryption Key Destruction For Secure Data Erasure
Application:
61/383,017 →
Adaptive ECC Techniques for Flash Memory Based Data Storage
Application:
61/407,178 →
Dynamic Higher-Level Redundancy Mode Management with Independent Silicon Elements
Application:
61/418,846 →
Cross-Decoding for Non-Volatile Storage
Application:
61/422,198 →
Higher-Level Redundancy Information Computation
Application:
61/433,918 →
Selective Enablement Of Status Coalescing Via Host Transfer Rate Detection
Application:
61/440,710 →
Variable Over-Provisioning For Non-Volatile Storage
Application:
61/479,249 →
Encrypted-Transport Solid-State Disk Controller
Application:
61/480,518 →
Management Of Device Firmware Update Effects As Seen By A Host
Application:
61/494,262 →
Scalable Storage Devices
Application:
61/497,525 →
Techniques For Secure Storage Hijacking Protection
Application:
61/511,989 →
I/O Device and Computing Host Interoperation
Application:
61/521,739 →
I/O Device and Computing Host Interoperation
Application:
61/531,551 →
I/O Device and Computing Host Interoperation
Application:
61/543,666 →
Self-Journaling and Hierarchical Consistency for Non-Volatile Storage
Application:
61/543,707 →
System for Accelerating Parallel Magnetic Resonance Imaging Reconstruction Using Joint Estimation with a Sparse Signal Model
Application:
61/599,201 →
Fractional Redundant Array of Silicon Independent Elements
Application:
61/682,561 →
Policy for flash memory read operations
Application:
61/735,908 →
Error correction code rate management for flash memory
Application:
61/735,917 →
Flash memory read error recovery policy with soft-decision LDPC decoder
Application:
61/735,923 →
Storage Address Space to Nvm Address, Span, and Length Mapping/Converting
Application:
61/755,169 →
Management of and Region Selection for Writes to Non-Volatile Memory
Application:
61/755,442 →
Non-Deterministic Encryption
Application:
61/755,951 →
Decoupled Locking Dma Architecture
Application:
61/758,770 →
Retention-Drift-History-Based Non-Volatile Memory Read Threshold Optimization
Application:
61/762,955 →
Storage Device Power Failure Infrastructure
Application:
61/775,651 →
Tamper Sensor
Application:
61/780,980 →
I/O Device with Multi-Reducible-Unit Mapping
Application:
61/782,089 →
Storage Device Assisted Data De-Duplication
Application:
61/782,122 →
Trim Mechanism Using Multi-Level Mapping in a Solid-State Media
Application:
61/783,555 →
Enhanced Queue Management
Application:
61/786,073 →
Lock-Free Communication Storage Request Reordering
Application:
61/786,170 →
Device Sleep Partitioning and Keys
Application:
61/789,337 →
Method of Optimizing Solid State Drive Soft Retry Voltages
Application:
61/804,853 →
Systems and Methods for Inter-cell Interference Mitigation in a Flash Memory
Application:
61/826,464 →
Variable Redundancy in a Solid State Drive
Application:
61/827,190 →
Sequential Read Optimized Variable-Sized Flash Translation Layer
Application:
61/866,672 →
Virtual Bands Concentration for Self Encrypting Drives
Application:
61/870,936 →
Translation Layer Partitioned Between a Host and a Controller
Application:
61/873,357 →
Systems and Methods for Enhanced Data Recovery in a Solid State Memory System
Application:
61/883,123 →
Flash Memory Reference Voltage Detection with Tracking of Cross-Points of Cell Voltage Distributions Using Histograms
Application:
61/883,491 →
Flash Memory Read Retry Using Histograms
Application:
61/886,180 →
Variable-Size Flash Translation Layer
Application:
61/888,681 →
Generating Soft Decoding Information for Flash Memory Error Correction Using Hard Decision Patterns
Application:
61/892,328 →
Systems and Methods for Latency Based Data Recycling in a Solid State Memory System
Application:
61/892,429 →
Systems and Methods for Soft Data Utilization in a Solid State Memory System
Application:
61/893,335 →
Translation Layer Partitioned Between Host and Controller
Application:
61/893,383 →
Systems and Methods for Sub-Zero Threshold Characterization in a Memory Cell
Application:
61/896,590 →
Method to Implement Unaligned Data Bands in a Self Encrypting Solid State Drive
Application:
61/897,366 →
Reduction or Elimination of Latency Penalty Associated with Adjusting Read Thresholds for Non-Volatile Memory
Application:
61/898,947 →
Systems and Methods for Soft Decision Generation in a Solid State Memory System
Application:
61/905,185 →
Eliminating or Reducing Programming Errors When Programming Flash Memory Cells
Application:
61/909,211 →
Non-Volatile Memory With Channel Tracking-Based Retry Read Voltage
Application:
61/909,447 →
Decoding with Log Likelihood Ratios Stored in a Controller
Application:
61/909,529 →
Bit-Line Defect Detection Using Unsatisfied Parity Checks
Application:
61/909,540 →
Flash Channel With Selective Decoder Likelihood Dampening
Application:
61/910,100 →
Multiple Retry Reads in a Read Channel of a Memory
Application:
61/914,056 →
Preventing Programming Errors from Occurring When Programming Flash Memory Cells
Application:
61/918,778 →
Systems and Methods for Hard Error Reduction in a Solid State Memory Device
Application:
61/936,599 →
Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus
Application:
61/937,040 →
Systems and Methods for Last Written Page Handling in a Memory Device
Application:
61/938,241 →
SYSTEM TO CONTROL A WIDTH OF A PROGRAMMING THRESHOLD VOLTAGE DISTRffiUTION WIDTH WHEN WRITING HOT-READ DATA
Application:
61/940,561 →
Periodically Updating a Log Likelihood Ratio (Llr) Table in a Flash Memory Controller
Application:
61/945,268 →
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 23, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 027916/0623 →
Assignment of Assignor's Interest
Jun 22, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028426/0212 →
Assignment of Assignor's Interest
Jun 22, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028427/0932 →
Assignment of Assignor's Interest
Jun 22, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028428/0200 →
Assignment of Assignor's Interest
Jun 25, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028434/0200 →
Assignment of Assignor's Interest
Aug 10, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028768/0297 →
Assignment of Assignor's Interest
Sep 11, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028938/0413 →
Assignment of Assignor's Interest
May 17, 2013
From: COHEN, EARL T; CANEPA, TIMOTHY L
To: LSI CORPORATION
Reel/Frame 030441/0898 →
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Assignment of Assignor's Interest
Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034776/0363 →
Assignment of Assignor's Interest
Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0272 →
Assignment of Assignor's Interest
Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034775/0777 →
Assignment of Assignor's Interest
Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034778/0763 →
Assignment of Assignor's Interest
Jan 22, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034782/0657 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →