IP Library Granted Patent US 9,170,742
Granted Patent B2
US 9,170,742 · App. 14/201,020 · Granted Oct 27, 2015

Techniques for reducing memory write operations using coalescing memory buffers and difference information

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Quick Facts
Patent No.
US 9,170,742
App. No.
14/201,020
Granted
Oct 27, 2015
Kind
B2
Abstract

A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.

Claims (41)

1. An apparatus comprising:

a difference computation module;

one or more coalescing memory buffers;

wherein the difference computation module is enabled to

receive a command initiating an operation to be applied to storage devices,

identify the operation as a write operation directed to one or more of a plurality of blocks of the storage devices,

compute a difference between a current state of data of the one or more blocks and a state that would result from the write operation, and

populate at least one of the coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks;

wherein the coalescing memory buffers are separate from the storage devices; and

wherein the difference computation module is further enabled to selectively write the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers.

2. The apparatus of claim 1 , wherein the difference computation module is further enabled to reconstruct a current state of data of the one or more blocks.

3. The apparatus of claim 1 , wherein the command is from a host processor, and the apparatus is coupled between the host processor and the storage devices.

4. The apparatus of claim 1 , wherein the difference information includes a location of the write operation.

5. The apparatus of claim 1 , wherein the difference computation module is separate from the storage devices.

6. The apparatus of claim 1 , wherein at least one of the storage devices comprises flash memory.

7. A method comprising:

via a difference computation module,

receiving a command initiating an operation to be applied to storage devices,

identifying the operation as a write operation directed to one or more of a plurality of blocks of the storage devices,

computing a difference between a current state of data of the one or more blocks and a state that would result from the write operation, and

populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks;

wherein the coalescing memory buffers are separate from the storage devices; and

further comprising, via the difference computation module, selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers.

8. The method of claim 7 , further comprising, via the difference computation module, reconstructing a current state of data of the one or more blocks.

9. The method of claim 7 , wherein the command is from a host processor, and the difference computation module and the coalescing memory buffers are coupled between the host processor and the storage devices.

10. The method of claim 7 , wherein the difference information includes a location of the write operation.

11. The method of claim 7 , wherein the difference computation module is separate from the storage devices.

12. The method of claim 7 , wherein at least one of the storage devices comprises flash memory.

13. A non-transitory computer readable medium having a set of instructions stored therein which when executed by a processing device causes the processing device to perform procedures comprising:

via a difference computation module,

receiving a command initiating an operation to be applied to storage devices,

identifying the operation as a write operation directed to one or more of a plurality of blocks of the storage devices,

computing a difference between a current state of data of the one or more blocks and a state that would result from the write operation, and

populating at least one of one or more coalescing memory buffers with difference information associated with the difference and to be used to update an associated one of the blocks;

wherein the coalescing memory buffers are separate from the storage devices; and

wherein the procedures further comprise, via the difference computation module, selectively writing the difference information in the coalescing memory buffers to the storage devices, based on a determination of fullness of the coalescing memory buffers.

14. The non-transitory computer readable medium of claim 13 , wherein the procedures further comprise, via the difference computation module, reconstructing a current state of data of the one or more blocks.

15. The non-transitory computer readable medium of claim 13 , wherein the command is from a host processor, and the difference computation module and the coalescing memory buffers are coupled between the host processor and the storage devices.

16. The non-transitory computer readable medium of claim 13 , wherein the difference information includes a location of the write operation.

17. The non-transitory computer readable medium of claim 13 , wherein the difference computation module is separate from the storage devices.

18. The non-transitory computer readable medium of claim 13 , wherein at least one of the storage devices comprises flash memory.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034774/0418 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →