Multiple retry reads in a read channel of a memory
View Patent ↗An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
1. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory; and
a control circuit configured to (i) adjust an initial one of a plurality of read voltages in a read channel of the memory by shifting the initial read voltage an amount toward a center of a window, (ii) read a codeword from the memory a number of times and (iii) generate read data by an iterative decode of the codeword based on the reads, wherein (a) the window bounds a range of the read voltages, (b) each of the reads uses a different one of the read voltages according to a pattern, (c) the pattern is symmetrically spaced about the initial read voltage as shifted such that the read voltages of consecutive reads are on opposite sides of the initial read voltage and (d) the pattern fits in the window.
2. The apparatus according to claim 1 , wherein (i) the control circuit is further configured to use a plurality of soft log likelihood ratio values in the iterative decode and (ii) the soft log likelihood ratio values are based on the number of times that the codeword is read.
3. The apparatus according to claim 2 , wherein (i) a plurality of original log likelihood ratio values and a plurality of modified log likelihood ratio values are stored concurrently in one or more lookup tables, (ii) the original log likelihood ratio values are used as the soft log likelihood ratio values when the initial read voltage is unshifted in the window and (iii) the modified log likelihood ratio values are use as the soft log likelihood ratio values when the initial read voltage is shifted toward the center of the window.
4. The apparatus according to claim 2 , further comprising one or more lookup tables configured to store a plurality of original log likelihood ratio values, wherein the soft log likelihood ratio values are generated in the control circuit by adjusting the original log likelihood ratio values based on the amount that the initial read voltage is shifted.
5. The apparatus according to claim 1 , wherein the read voltages in the pattern are evenly spaced from each other by a uniform voltage value.
6. The apparatus according to claim 5 , wherein the initial read voltage is shifted when the initial read voltage prior to the shift is less than a predetermined multiple of the uniform voltage value from an edge of the window.
7. The apparatus according to claim 1 , wherein the memory is a nonvolatile memory.
8. The apparatus according to claim 1 , wherein the apparatus is implemented as one or more integrated circuits.
9. A method for multiple read retries in a read channel, comprising the steps of:
adjusting an initial one of a plurality of read voltages in the read channel of a memory by shifting the initial read voltage an amount toward a center of a window, wherein the window bounds a range of the read voltages;
reading a codeword from the memory a number of times, wherein (i) each of the reads uses a different one of the read voltages according to a pattern, (ii) the pattern is symmetrically spaced about the initial read voltage as shifted such that the read voltages of consecutive reads are on opposite sides of the initial reference voltage and (iii) the pattern fits in the window; and
generating read data by an iterative decode of the codeword based on the reads.
10. The method according to claim 9 , further comprising the step of:
using a plurality of soft log likelihood ratio values in the iterative decode, wherein the soft log likelihood ratio values are based on the number of times that the codeword is read.
11. The method according to claim 10 , wherein (i) a plurality of original log likelihood ratio values and a plurality of modified log likelihood ratio values are stored concurrently in one or more lookup tables, (ii) the original log likelihood ratio values are used as the soft log likelihood ratio values when the initial read voltage is unshifted in the window and (iii) the modified log likelihood ratio values are use as the soft log likelihood ratio values when the initial read voltage is shifted toward the center of the window.
12. The method according to claim 10 , further comprising the step of:
generating the soft log likelihood ratio values by adjusting a plurality of original log likelihood ratio values based on the amount that the initial read voltage is shifted, wherein the original log likelihood ratio values are stored in one or more lookup tables.
13. The method according to claim 9 , wherein the read voltages in the pattern are evenly spaced from each other by a uniform voltage value.
14. The method according to claim 13 , wherein the initial reference voltage is shifted when the initial read voltage prior to the shift is less than a predetermined multiple of the uniform voltage value from an edge of the window.
15. The method according to claim 9 , wherein the memory is a nonvolatile memory.
16. The method according to claim 10 , further comprising the steps of:
storing a plurality of original log likelihood ratio values in one or more lookup tables; and
generating the soft log likelihood ratio values by adjusting the original log likelihood ratio values based on the amount that the initial read voltage is shifted.
17. The method according to claim 9 , wherein the method is implemented in a memory controller.
18. The apparatus according to claim 1 , wherein the interface and the control circuit are part of a memory controller.
19. An apparatus comprising:
a nonvolatile memory configured to process a plurality of read/write operations; and
a controller configured to (i) adjust an initial one of a plurality of read voltages in a read channel of the nonvolatile memory by shifting the initial read voltage an amount toward a center of a window, (ii) read a codeword from the memory a number of times and (iii) generate read data by an iterative decode of the codeword based on the reads, wherein (a) the window bounds a range of the read voltages, (b) each of the reads uses a different one of the read voltages according to a pattern, (c) the pattern is symmetrically spaced about the initial read voltage as shifted such that the read voltages of consecutive reads are on opposite sides of the initial read voltage and (d) the pattern fits in the window.
20. The apparatus according to claim 19 , wherein the nonvolatile memory and the controller are part of a solid-state drive.