Bit-line defect detection using unsatisfied parity code checks
View Patent ↗An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.
1. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory, wherein a plurality of bit-lines in the memory are used to access each of at least two codewords; and
a control circuit configured to (i) generate a syndrome during a decode of a first of the at least two codewords, (ii) update a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines in the memory, and (iii) decode a second of the at least two codewords in response to the map of defects.
2. The apparatus according to claim 1 , wherein the control circuit is further configured to update a respective count value of each of the plurality of bits in the map of defects according to a respective number of unsatisfied parity checks derived from the syndrome.
3. The apparatus according to claim 2 , wherein the circuit is further configured to detect defective ones of the plurality of bit-lines based on one or more of (i) the respective count values and (ii) a history of states of the plurality of bit-lines.
4. The apparatus according to claim 2 , wherein the control circuit is further configured to reduce a false detection rate by filtering the respective count values.
5. The apparatus according to claim 1 , wherein the map of defects is generated where decoding of a previous codeword fails to converge.
6. The apparatus according to claim 1 , wherein the memory is nonvolatile.
7. The apparatus according to claim 1 , wherein the at least two codewords are decoded by a low density parity check decode.
8. The apparatus according to claim 1 , wherein the control circuit is further configured to (i) utilize each of a plurality of code rates in the decode of the first codeword, (ii) identify a given one of the plurality of code rates used to encode the first codeword in the memory and (iii) generate a bit error rate of the memory based on the syndrome.
9. The apparatus according to claim 1 , wherein the apparatus is implemented as one or more integrated circuits.
10. The apparatus according to claim 1 , wherein the memory and the control circuit are part of a solid-state drive.
11. A method for bit-line defect detection using unsatisfied parity code checks, comprising the steps of:
receiving at least two codewords at a circuit from a memory, wherein a plurality of bit-lines in the memory are used to access each of the at least two codewords;
generating a syndrome during a decode of a first of the at least two codewords;
updating a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines of the memory; and
decoding a second of the at least two codewords in response to the map of defects.
12. The method according to claim 11 , further comprising the step of:
updating a respective count value of each of the plurality of bits in the map of defects according to a respective number of unsatisfied parity checks derived from the syndrome.
13. The method according to claim 12 , further comprising the step of:
detecting defective ones of the plurality of bit-lines of the memory based on one or more of (i) the respective count values and (ii) a history of states of the plurality of bit-lines.
14. The method according to claim 12 , further comprising the step of:
reducing a false detection rate by filtering the respective count values.
15. The method according to claim 11 , wherein the map of defects is generated where decoding of a previous codeword fails to converge.
16. The method according to claim 11 , wherein the memory and the circuit are part of a solid-state drive.
17. The method according to claim 11 , wherein the at least two codewords are decoded by a low density parity check decode.
18. The method according to claim 11 , further comprising the steps of:
utilizing each of a plurality of code rates in the decode of the first codeword;
identifying a given one of the plurality of code rates used to encode the first codeword in the memory; and
generate a bit error rate of the memory based on the syndrome.
19. An apparatus comprising:
a memory configured to store data, wherein a plurality of bit-lines in the memory are used to access each of at least two codewords from among the data; and
a controller configured to (i) process a plurality of input/output requests to read/write to/from the memory, (ii) receive the at least two codewords from the memory, (iii) generate a syndrome during a decode of a first of the at least two codewords, (iv) update a map of defects in the memory according to the syndrome, wherein each of a plurality of bits in the map of defects corresponds to a respective one of the plurality of bit-lines in the memory, and (v) decode a second of the at least two codewords in response to the map of defects.
20. The apparatus according to claim 19 , wherein the memory and the controller are part of a solid-state drive.