IP Library Granted Patent US 8,711,620
Granted Patent B2
US 8,711,620 · App. 13/588,043 · Granted Apr 29, 2014

Memory device having collaborative filtering to reduce noise

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Quick Facts
Patent No.
US 8,711,620
App. No.
13/588,043
Granted
Apr 29, 2014
Kind
B2
Abstract

An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.

Claims (28)

1. An apparatus comprising:

a collaborative filtering circuit configured to communicatively couple to a memory array, the memory array having a plurality of memory cell blocks and configured to furnish a signal representative of data stored within the plurality of memory cell blocks,

wherein the collaborative filtering circuit is configured to determine a noise distribution associated with the plurality of memory cell blocks and to generate a noise prediction when a read operation for the plurality of memory cell blocks is issued, the noise prediction based upon the noise distribution.

2. The apparatus as recited in claim 1 , wherein the collaborative filtering circuit is configured to compensate the signal utilizing the noise prediction.

3. The apparatus as recited in claim 2 , wherein the collaborative filtering circuit is configured to modify the signal to at least substantially remove noise from the signal.

4. The apparatus as recited in claim 2 , wherein the noise comprises at least one of a random-telegraph noise, a retention process noise, an inter-cell interference noise, a background pattern noise, or a read/program disturbance noise.

5. The apparatus as recited in claim 1 , wherein the plurality of memory cell blocks comprise a plurality of non-volatile memory cell blocks.

6. The apparatus as recited in claim 5 , wherein the plurality of non-volatile memory cell blocks comprise a plurality of NAND memory cell blocks.

7. The apparatus as recited in claim 6 , wherein the plurality of NAND memory cell blocks comprise a plurality of NAND multi-level memory cell blocks, each NAND multi-level memory cell within the plurality of NAND multi-level memory cell blocks configured to store more than a single bit of data.

8. A storage device comprising:

a memory array having a plurality of memory cell blocks, the memory array configured to furnish a signal representative of data stored within the plurality of memory cell blocks;

a read/write channel configured to determine a noise value associated with a first memory cell block of the plurality of memory cell blocks during a first read operation; and

a collaborative filtering module communicatively coupled to the memory array and the read/write channel, the collaborative filtering module configured to receive the noise value from the read/write channel to determine a noise distribution associated with the first memory cell block of the plurality of memory cell blocks and to generate a noise prediction when a second read operation for the first memory cell block of the plurality of memory cell blocks is issued, the noise prediction based upon the noise distribution.

9. The storage device as recited in claim 8 , wherein the collaborative filtering module is configured to compensate the signal utilizing the noise prediction.

10. The storage device as recited in claim 9 , wherein the collaborative filtering module is configured to modify the signal to at least substantially remove noise from the signal.

11. The storage device as recited in claim 9 , wherein the noise comprises at least one of a random-telegraph noise, a retention process noise, an inter-cell interference noise, a background pattern noise, or a read/program disturbance noise.

12. The storage device as recited in claim 8 , wherein the plurality of memory cell blocks comprise a plurality of non-volatile memory cell blocks.

13. The storage device as recited in claim 12 , wherein the plurality of non-volatile memory cell blocks comprise a plurality of NAND memory cell blocks.

14. The storage device as recited in claim 13 , wherein the plurality of NAND memory cell blocks comprise a plurality of NAND multi-level memory cell blocks, each NAND multi-level memory cell within the plurality of NAND multi-level memory cell blocks configured to store more than a single bit of data.

15. A method comprising:

calculating a noise distribution associated with a first block of memory cells of an array of memory cells after an issuance of a first read operation to the first block of memory cells;

generating a noise prediction based upon the noise distribution when a second read operation to the first block of memory cells is issued, the noise prediction generated by a collaborative filtering module; and

compensating a noise portion of a signal utilizing the noise prediction.

16. The method as recited in claim 15 , wherein the signal represents data stored within the first block of memory cells.

17. The method as recited in claim 15 , wherein compensating the noise portion further comprises modifying a signal to at least substantially remove a noise portion from the signal.

18. The method as recited in claim 15 , wherein the first block of memory cells comprises a first block of non-volatile memory cells.

19. The method as recited in claim 18 , wherein the first block of non-volatile memory cells comprises a first block of NAND memory cells.

20. The method as recited in claim 15 , wherein the noise portion comprises at least one of a random-telegraph noise portion, a retention process noise portion, an inter-cell interference noise portion, a background pattern noise portion, or a read/program disturbance noise portion.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034775/0777 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2012
From: ZHANG, FAN; ALHUSSIEN, ABDELHAKIM S.; LI, ZONGWANG; HARATSCH, ERICH F.
To: LSI CORPORATION
Reel/Frame 028803/0369 →