Non-deterministic encryption
View Patent ↗A non-deterministic encryption functionality receives and encrypts an open-text input stream. Codes for error-correction are generated for the encrypted stream, and a correctable amount of non-deterministic random error is overlaid onto the encrypted stream and the codes for error-correction. The error-injected encrypted stream and codes for error-correction are re-encrypted and delivered to a using process. A non-deterministic decryption functionality reverses the encryption, in some embodiments using key values used during the encryption, and delivers an open-text stream to a using process. Some embodiments of a non-deterministic encryption include a reversible scrambling layer. In some embodiments, the non-deterministic encryption and decryption functionalities are performed, at least in part, by a controller of a solid state disk. In some embodiments, the functionalities are performed within a secure physical boundary provided by implementation within a single integrated circuit.
1. A method comprising:
receiving unencrypted data from a computing host;
encrypting the received unencrypted data to create a first cipher text with a first encryption key;
generating one or more error-correction codes in response to the first cipher text;
applying a first error mask to the error-correction codes and a second error mask to the first cipher text to inject a correctable non-deterministic error into each of the first cipher text and the error-correction codes;
re-encrypting a combination of the error-injected first cipher text and error-correction codes with a second encryption key to create a single second cipher text; and
formatting the single second cipher text wherein formatting comprises scrambling and modulating, to be compatible with storage in one or more non-volatile memories (NVMs), wherein the receiving, encrypting, generating, applying, re-encrypting, and formatting are each executed by a controller of a storage device comprising the NVMs.
2. The method of claim 1 , further comprising:
the encrypting and the re-encrypting employing a symmetric encryption standard and the first encryption key is different from the second encryption key.
3. The method of claim 2 , further comprising:
performing the receiving, encrypting, generating, applying, and re-encrypting within a secure physical boundary.
4. The method of claim 3 , wherein the secure physical boundary comprises a single integrated circuit.
5. The method of claim 4 , further comprising:
saving the first and second encryption keys within the secure physical boundary.
6. The method of claim 1 , further comprising:
receiving a storage address from the computing host, and storing the formatted single second cipher text in the NVMs in accordance with the storage address.
7. The method of claim 1 , wherein the receiving is via a storage interface compatible with a storage interface standard.
8. The method of claim 1 , wherein the first error mask conducts a first logical operation comparing the first cipher text to a first constrained pseudo-random number and the second error mask conducts a second logical operation comparing the error-correction codes to a second constrained pseudo-random number, each constrained pseudo-random number generated from a non-deterministic key.
9. The method of claim 1 , wherein the error-correction codes undergo a logically function to combine a counter value with the error-correction codes prior to application of the second error mask.
10. A method comprising:
receiving a storage address from a computing host;
importing raw data from one or more non-volatile memories (NVMs) in accordance with the storage address; correcting low-level errors on the raw data, based on low-level error-correction information contained therein, producing corrected data;
unformatting the corrected data;
decrypting the unformatted data with a first encryption key to create a first cipher text;
partitioning the first cipher text into a data portion and an error-correction portion, the data portion comprising a second cipher text and a first error mask, the error-correction portion comprising error-correction codes and a second error mask;
correcting injected errors of the first and second error masks to produce a second cipher text wherein the correcting injected errors on the data portion comprises processing portions of the data portion according to a first chunk size, the re-decrypting the error corrected data portion comprises processing the error corrected data portion according to a second chunk size, and the first and the second chunk sizes are different;
re-decrypting the second cipher text with a second encryption key; and exporting the second cipher text to the computing host, wherein the receiving, importing, low-level error correcting, unformatting, decrypting, partitioning, injected error correcting, re-encrypting, and exporting are each executed by a controller of a storage device comprising the NVMs.
11. The method of claim 10 , wherein the first and second encryption keys are different.
12. The method of claim 10 , wherein the first error mask overlays a first binary logic operation and the second error mask overlays a different second logic operation.
13. The method of claim 12 , wherein the first binary logic operation is a logical XOR.
14. The method of claim 12 , wherein the second binary operation is a logical AND.
15. The method of claim 10 , wherein the correcting step combines the data and error-correction portions into a single data stream of the second cipher text.
16. The method of claim 10 , wherein the raw data is reverse scrambled prior to being decrypted with the first encryption key.
17. The method of claim 10 , wherein the error-correction portion is combined with an exclusive-OR function to recover injected errors.