IP Library Granted Patent US 7,904,672
Granted Patent B2
US 7,904,672 · App. 11/942,629 · Granted Mar 8, 2011

System and method for providing data redundancy after reducing memory writes

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Quick Facts
Patent No.
US 7,904,672
App. No.
11/942,629
Granted
Mar 8, 2011
Kind
B2
Abstract

A system, method, and computer program product are provided for providing data redundancy in a plurality of storage devices. In operation, a number of writes to a plurality of storage devices is reduced. Additionally, after the reducing, data redundancy is provided utilizing a data redundancy scheme.

Claims (30)

1. A method, comprising:

receiving writes from a computer via a standard storage subsystem interface;

reducing a number of the received writes; implementing, via a disk controller, a data redundancy scheme comprising storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory; and

wherein the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

2. The method as recited in claim 1 , wherein the data redundancy scheme includes a redundant array of independent disks (RAID) data redundancy scheme.

3. The method as recited in claim 2 , wherein the data redundancy scheme includes a redundant array of independent disks (RAID)-5 data redundancy scheme.

4. The method as recited in claim 2 , wherein the data redundancy scheme includes a redundant array of independent disks (RAID)-6 data redundancy scheme.

5. The method as recited in claim 1 , wherein the standard storage subsystem interface comprises a SATA interface.

6. The method as recited in claim 5 , wherein the disk controller is included in a disk drive.

7. The method as recited in claim 1 , wherein the storage subsystem interface comprises a SAS interface.

8. The method as recited in claim 7 , wherein the disk controller is included in a disk drive.

9. The method as recited in claim 1 , wherein at least one of the flash memories comprises NAND flash memory.

10. The method as recited in claim 9 , wherein the NAND flash memory includes single-level cell (SLC) NAND flash memory.

11. The method as recited in claim 9 , wherein the NAND flash memory includes multi-level cell (MLC) NAND flash memory.

12. The method as recited in claim 1 , wherein the flash memories are included in a disk drive.

13. The method as recited in claim 1 , and further comprising detecting a disconnection of a power source of the disk controller.

14. The method as recited in claim 13 , and further comprising providing power to the disk controller, in response to the detection of the disconnection of the power source.

15. The method as recited in claim 14 , wherein power is provided to the disk controller until at least a point when no data loss will occur as a result of the disconnection of the power source.

16. The method as recited in claim 15 , wherein the power is provided utilizing a capacitor.

17. The method as recited in claim 15 , wherein the power is provided utilizing a battery.

18. The method as recited in claim 1 , wherein the disk controller and the flash memories are included in a disk drive.

19. A computer program product embodied on a computer readable medium, comprising:

computer code for reducing a number of writes to a storage subsystem;

computer code for providing data redundancy utilizing a data redundancy scheme, after the reducing; and

wherein the writes are received from a computer via a standard storage subsystem interface, the data redundancy scheme is implemented by a disk controller and comprises storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory, and the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

20. An apparatus, comprising:

a circuit enabled to receive writes from a computer via a standard storage subsystem interface, and further enabled to reduce a number of the received writes;

a disk controller that implements a data redundancy scheme comprising storing data associated with the reduced number of writes in a plurality of primary flash memories and storing computed redundant information in at least one redundant flash memory; and

wherein the disk controller is enabled to operate without a loss of data in the presence of at least a single failure of any of the flash memories.

21. The apparatus as recited in claim 20 , and further comprising a the primary and the redundant flash memories.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034775/0777 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2012
From: SANDFORCE, INC.
To: LSI CORPORATION
Reel/Frame 028938/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2007
From: DANILAK, RADOSLAV
To: SANDFORCE, INC.
Reel/Frame 020141/0641 →