Accelerated soft read for multi-level cell nonvolatile memories
A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. The given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.
1. A memory device comprising:
a memory array comprising a plurality of multi-level memory cells; and
control circuitry coupled to the memory array and configured to perform accelerated soft read operations on at least a portion of the memory array;
wherein a given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises a lower page soft read operation, wherein the lower page soft read operation comprises a sequence of multiple hard read operations, the sequence of multiple hard read options comprising a first hard read operation directed to the non-upper page of the memory array, and at least a second hard read operation directed to a corresponding upper page of the memory array;
wherein a read output decision for the given accelerated soft read operation directed to the non-upper page of the memory array is based on upper page soft information obtained at least in part from the second hard read operation directed to the corresponding upper page of the memory array;
wherein the upper page soft information comprises information indicating a strength of a result obtained from the first hard read operation directed to the non-upper page of the memory array; and
wherein the second hard read operation directed to the corresponding upper page of the memory array comprises a hard read of the upper page of the memory array.
2. The memory device of claim 1 wherein the second hard read operation directed to the corresponding upper page has multiple voltage reference values associated therewith.
3. The memory device of claim 1 wherein the second hard read operation directed to the corresponding upper page is performed utilizing a predetermined command established by a vendor of the memory array.
4. The memory device of claim 1 wherein the control circuitry comprises:
a soft read accelerator configured to specify the sequence of hard read operations to be performed as part of the given accelerated soft read operation;
a soft information generator configured to perform the specified sequence of hard read operations to obtain the soft information for the accelerated soft read operation; and
a soft-decision error correction code decoder coupled to the soft information generator and configured to generate the read output decision based on the soft information obtained for the accelerated soft read operation.
5. The memory device of claim 1 wherein the multi-level memory cells comprise two-level memory cells each storing two bits of data.
6. The memory device of claim 1 wherein the multi-level memory cells comprise three-level memory cells each storing three bits of data.
7. The memory device of claim 6 wherein the given accelerated soft read operation comprises one of a middle page soft read operation and a lower page soft read operation.
8. The memory device of claim 7 wherein the middle page soft read operation comprises:
a first hard read operation directed to a middle page; and
at least one additional hard read operation directed to an upper page.
9. The memory device of claim 7 wherein the lower page soft read operation comprises:
the first hard read operation directed to a lower page; and
at least one additional hard read operation directed to an upper page.
10. The memory device of claim 7 wherein the lower page soft read operation comprises:
the first hard read operation directed to a lower page; and
at least one additional hard read operation directed to a middle page.
11. The memory device of claim 1 wherein the non-upper page comprises a first portion of a set of bits for a designated group of the multi-level memory cells and the upper page comprises a second portion of the set of bits for the designated group of multi-level memory cells.
12. The memory device of claim 11 wherein the designated group comprises a designated row of the multi-level memory cells.
13. An integrated circuit comprising the memory device of claim 1 .
14. A processing device comprising the memory device of claim 1 .
15. The memory device of claim 1 wherein the given accelerated soft read operation directed to the non-upper page of the memory array comprises:
obtaining at least one hard decision value for the corresponding upper page; and
utilizing the at least one hard decision value to generate the upper page soft information.
16. The memory device of claim 1 wherein the second hard read operation directed to the corresponding upper page of the memory array:
utilizes at least a first pair of reference voltages;
returns a first value if a threshold voltage is between the first pair of reference voltages; and
returns a second value different than the first value if the threshold voltage is outside the first pair of reference voltages.
17. The memory device of claim 16 wherein:
the first hard read operation directed to the non-upper page of the memory array utilizes a first reference voltage; and
the first pair of reference voltages comprises a second reference voltage lower than the first reference voltage and a third reference voltage higher than the first reference voltage.
18. A method comprising:
determining one or more accelerated soft read operations to be performed on at least a portion of a memory array comprising a plurality of multi-level memory cells; and
performing at least a given one of the accelerated soft read operations;
wherein the given accelerated soft read operation is directed to a non-upper page of the memory array and comprises a lower page soft read operation, wherein the lower page soft read operation comprises a sequence of multiple hard read operations, the sequence of multiple hard read options comprising a first hard read operation directed to the non-upper page of the memory array, and at least a second hard read operation directed to a corresponding upper page of the memory;
wherein a read output decision for the given accelerated soft read operation directed to the non-upper page of the memory array is based on soft information obtained at least in part from the second hard read operation directed to the corresponding upper page of the memory array;
wherein the upper page soft information comprises information indicating a strength of a result obtained from the first hard read operation directed to the non-upper page of the memory array; and
wherein the second hard read operation directed to the corresponding upper page of the memory array comprises a hard read of the upper page of the memory array.
19. The method of claim 18 wherein the second hard read operation directed to the corresponding upper page of the memory array:
utilizes at least a first pair of reference voltages;
returns a first value if a threshold voltage is between the first pair of reference voltages; and
returns a second value different than the first value if the threshold voltage is outside the first pair of reference voltages.
20. An apparatus comprising:
control circuitry adapted for coupling to a memory array comprising a plurality of multi-level memory cells;
the control circuitry being configured to perform accelerated soft read operations on at least a portion of the memory array;
wherein a given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises a lower page soft read operation, wherein the lower page soft read operation comprises a sequence of multiple hard read operations, the sequence of multiple hard read options comprising a first hard read operation directed to the non-upper page of the memory array, and at least a second hard read operation directed to a corresponding upper page of the memory array;
wherein a read output decision for the given accelerated soft read operation directed to the non-upper page of the memory array is based on soft information obtained at least in part from the second hard read operation directed to the corresponding upper page of the memory array;
wherein the upper page soft information comprises information indicating a strength of a result obtained from the first hard read operation directed to the non-upper page of the memory array; and
wherein the second hard read operation directed to the corresponding upper page of the memory array comprises a hard read of the upper page of the memory array.
21. The apparatus of claim 20 wherein the control circuitry comprises:
a soft read accelerator configured to specify the sequence of hard read operations to be performed as part of the given accelerated soft read operation;
a soft information generator configured to perform the specified sequence of hard read operations to obtain the soft information for the accelerated soft read operation; and
a soft-decision error correction code decoder coupled to the soft information generator and configured to generate the read output decision based on the soft information obtained for the accelerated soft read operation.
22. The apparatus of claim 20 wherein the second hard read operation directed to the corresponding upper page of the memory array:
utilizes at least a first pair of reference voltages;
returns a first value if a threshold voltage is between the first pair of reference voltages; and
returns a second value different than the first value if the threshold voltage is outside the first pair of reference voltages.