Policy for read operations addressing on-the-fly decoding failure in non-volatile memory

1. An apparatus comprising:

a non-volatile memory; and

a controller operatively coupled to the non-volatile memory and comprising an error correction engine configured to perform error correction on codewords read from the non-volatile memory and, upon error correction failure, to perform one or more retry procedures, wherein the controller is configured to (i) perform read and write operations on the non-volatile memory using the codewords as a unit of read access, (ii) in response to the error correction failure or one or more of the retry procedures not being successful, perform one or more background procedures configured to determine a cause of the error correction failure, (iii) in response to determining the error correction failure is due to transient noise, eliminate the transient noise by recycling on a block or R-block granularity, and (iv) in response to all of the retry procedures not being successful, send an error message.

2. The apparatus according to claim 1 , wherein the non-volatile memory and the controller are configured as a solid state drive and the controller is enabled to be operatively coupled to a host system.

3. The apparatus according to claim 1 , wherein:

the error correction comprises a hard decision low-density parity-check (HDLDPC) decoding; and

the one or more retry procedures comprise one or more of (i) additional reads with a same or a different reference voltage (Vref), (ii) error correction code (ECC) re-decoding of different decoder inputs, parameters, or both inputs and parameters, (iii) soft decision low-density parity-check (SDLDPC) decoding, (iv) digital signal processing techniques, and (v) a higher-level redundancy function using a redundancy code.

4. The apparatus according to claim 1 , wherein the one or more background procedures comprise

noise source identification.

5. The apparatus according to claim 4 , wherein the noise source identification comprises one or more of:

a procedure to determine whether an R-block suffers from long retention; and

a procedure to determine whether a block suffers from an amount of read disturb greater than a predetermined threshold.

6. The apparatus according to claim 4 , wherein the noise source identification comprises one or more procedures to differentiate between error correction failures due to transient noise and error correction failures due to non-transient noise.

7. The apparatus according to claim 1 , wherein the recycling on a block or R-block granularity involves erasing the block or R-block.

8. The apparatus according to claim 6 , wherein the controller is configured to mitigate the non-transient noise by at least one of tracking of channel parameters and lowering code rate.

9. The apparatus according to claim 6 , wherein the controller is further configured to eliminate the non-transient noise by retiring a block or R-block that had the error correction failure.

10. A method of managing data in a non-volatile storage system comprising the steps of

reading a first data entry and error correction code (ECC) information associated with the first data entry;

performing an error correction procedure on the first data entry and the ECC information associated with the first data entry;

if the error correction fails, performing one or more retry procedures;

sending an error message in response to all of the retry procedures not being successful;

performing one or more background procedures in response to at least one of the retry procedures being successful, wherein the one or more background procedures are performed by the non-volatile storage system to determine a cause of the error correction failure; and

upon determining the error correction failure is due to transient noise, enabling the non-volatile storage system to eliminate the transient noise by recycling on a block or R-block granularity.

11. The method according to claim 10 , wherein the non-volatile storage system comprises at least one of:

a controller and a flash memory module made up of a plurality of flash memory devices;

a controller comprising a plurality of processors operatively coupled to a flash memory module made up of a plurality of flash memory devices; and

a controller operatively coupled (i) to a host via a host interface circuit and (ii) to a flash memory module made up of a plurality of flash memory devices via a flash interface circuit.

12. The method according to claim 10 , wherein:

the error correction procedure comprises a hard decision low-density parity-check (HDLDPC) decoding; and

the one or more retry procedures comprise one or more of (i) additional reads with a same or a different reference voltage (Vref), (ii) ECC re-decoding of different decoder inputs, parameters, or both inputs and parameters, (iii) soft decision low-density parity-check (SDLDPC) decoding, (iv) digital signal processing techniques, and (v) a higher-level redundancy function using a redundancy code.

13. The method according to claim 10 , wherein the one or more background procedures comprise

identifying a noise source.

14. The method according to claim 13 , wherein identifying the noise source comprises one or more of:

determining whether an R-block suffers from long retention; and

determining whether a block suffers from an amount of read disturb greater than a predetermined threshold.

15. The method according to claim 13 , wherein identifying the noise source comprises performing one or more procedures to differentiate between error correction failures due to transient noise and error correction failures due to non-transient noise.

16. The method according to claim 10 , wherein the recycling on a block or R-block granularity involves erasing the block or R-block.

17. The method according to claim 15 , further comprising enabling a controller to eliminate the non-transient noise by at least one of tracking of channel parameters, retiring a block or R-block that had the error correction failure, and lowering code rate.

18. The apparatus according to claim 1 , wherein:

the controller is further configured to retire a portion of the non-volatile memory associated with the error correction failure when the cause of the error correction failure is determined to be non-transient noise.

19. The apparatus according to claim 4 , wherein the one or more background procedures further comprise one or more of:

page-level recycling;

identification of page-to-page variation; and

code rate adjustment.

20. The method according to claim 13 , wherein the one or more background procedures further comprise one or more of:

page-level recycling;

identifying page-to-page variation; and

adjusting a code rate.