IP Library Granted Patent US 9,329,948
Granted Patent B2
US 9,329,948 · App. 13/620,982 · Granted May 3, 2016

Measuring cell damage for wear leveling in a non-volatile memory

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Quick Facts
Patent No.
US 9,329,948
App. No.
13/620,982
Granted
May 3, 2016
Kind
B2
Abstract

An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.

Claims (72)

1. A method comprising:

in a Non-Volatile Memory (NVM) comprising one or more portions, each of the one or more portions comprising one or more cells, detecting an initial error from at least one or more cells of a particular one of the one or more portions;

determining whether the initial error a particular error condition;

responsive to determining that the initial error is the particular error condition, reprogramming at least a sub-portion of the particular portion and reading back the at least one of the cells, the sub-portion comprising the at least one of the cells;

detecting whether the at least one of the cells reprogrammed and read back includes a subsequent error; and

responsive to detecting whether the at least one of the cells includes a subsequent error, recording that the particular error condition is a first type of error condition.

2. The method of claim 1 , wherein the first type of error is one or more of programming failure and erase failure.

3. The method of claim 1 , wherein the determining comprises applying forward error correction decoding to a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells.

4. The method of claim 1 , wherein the detecting of the subsequent error comprises reprogramming and/or erasing at least a sub-portion of the particular portion and reading back the at least one of the cells, the sub-portion comprising the at least one of the cells.

5. The method of claim 1 , further comprising:

detecting that the first type of error condition is a cell damage error;

measuring cell damage for the one or more of the cells; and

performing wear leveling on the one or more portions, based at least in part upon at least some results of the measuring, wherein the recording the particular error condition as the first type of error condition further comprises updating one or more cell damage counters associated with any one or more of:

the at least one of the cells,

a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells, and

the particular portion.

6. The method of claim 5 , wherein the performing comprises selecting ones of the portions to write based at least in part on values of the cell damage counters associated with the portions.

7. A system comprising:

a Non-Volatile Memory (NVM) comprising one or more portions, each of the one or more portions comprising one or more cells; and

a controller enabled to

detect an initial error from at least one or more cells of a particular one of the one or more cells,

determine whether the initial error from at least one of the one or more cells of a particular one of the one or more portions is a particular error condition,

responsive to determining that the initial error is the particular error condition, reprogram at least a sub-portion of the particular portion and read back the at least one of the cells, the sub-portion comprising the at least one of the cells,

detect whether the at least one of the cells reprogrammed and read back includes a subsequent error, and

responsive to detecting whether the at least one of the cells includes a subsequent error, record that the particular error condition is a first type of error condition.

8. The system of claim 7 , wherein the first type of error condition is one or more of programming failure and erase failure.

9. The system of claim 7 , wherein the controller is further enabled to apply forward error correction decoding to a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells.

10. The system of claim 7 , wherein the controller is further enabled to:

record that the first type of error condition is a cell damage error,

measure cell damage for the one or more of the cells, and

perform wear leveling on the one or more portions, based at least in part upon at least some results of the measuring cell damage, and

update one or more cell damage counters associated with any one or more of:

the at least one of the cells,

a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells, and

the particular portion.

11. The system of claim 10 , wherein the controller is further enabled to select ones of the portions to write based at least in part on values of the cell damage counters associated with the portions.

12. An apparatus comprising:

a Non-Volatile Memory (NVM) comprising one or more portions; each of the one or more portions comprising one or more cells;

measurement hardware logic circuitry enabled to detect an initial error for one or more of the cells, and

determine whether the initial error from at least one of the one or more cells of a particular one of one or more portions is a particular error condition;

retry hardware logic circuitry enabled to reprogram at least a sub-portion of the particular portion and read back the at least one of the cells responsive to the determination by the measurement hardware logic circuitry whether the initial error is the particular error condition, the sub-portion comprising the at least one of the cells; and

failure detection hardware logic circuitry enabled to

detect whether the at least one of the cells reprogrammed and read back includes a subsequent error, and

record that the particular error condition is a first type of error condition responsive to the detection of whether the at least one of the cells includes the subsequent error.

13. The apparatus of claim 12 , wherein the first type of error condition is one or more of programming failure and erase failure.

14. The apparatus of claim 12 , wherein the determination hardware logic circuitry comprises decode hardware logic circuitry enabled to apply forward error correction decoding to a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells.

15. The apparatus of claim 12 , further comprising:

damage detection hardware logic circuitry enabled to detect that the first type of error condition is a cell damage error;

wear level hardware logic circuitry enabled to perform wear leveling on the one or more portions, based at least in part upon at least some results of the measuring; and

counter hardware logic circuitry enabled to update one or more cell damage counters associated with any one or more of:

the at least one of the cells,

a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells, and

the particular portion.

16. The apparatus of claim 15 , wherein the wear level hardware logic circuitry comprises selection hardware logic circuitry enabled to select ones of the portions to write based at least in part on values of the cell damage counters associated with the portions.

17. A tangible computer readable medium having a set of instructions stored therein that when executed by a processing element cause the processing element to perform and/or control operations comprising:

in a Non-Volatile Memory (NVM) comprising one or more portions, each of the one or more portions comprising one or more cells,

detecting an initial error for one or more of the cells,

determining whether the initial error is a particular error condition;

reprogramming at least a sub-portion of the particular portion and reading back the at least one of the cells if the initial error is the particular error condition, the sub-portion comprising the at least one of the cells:

detecting whether the at least one of the cells reprogrammed and read back includes a subsequent error; and

responsive to detecting whether the at least one of the cells includes a subsequent error, recording that the particular error condition is first type of error condition.

18. The tangible computer readable medium of claim 17 , wherein the first type of error condition is one or more of programming failure and erase failure.

19. The tangible computer readable medium of claim 17 , wherein the determining comprises applying forward error correction decoding to a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells.

20. The tangible computer readable medium of claim 17 , detecting that the first type of error condition is a cell damage error;

measuring cell damage for the one or more of the cells; and

performing wear leveling on the portions, based at least in part upon at least some results of the measuring,

wherein the measuring further comprises updating one or more cell damage counters associated with any one or more of:

the at least one of the cells,

a sub-portion of the particular portion, the sub-portion comprising the at least one of the cells, and

the particular portion.

21. The tangible computer readable medium of claim 20 , wherein the performing comprises selecting ones of the portions to write based at least in part on values of the cell damage counters associated with the portions.

22. The tangible computer readable medium of claim 21 , wherein the selecting is further based upon a cell damage threshold.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0571 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2013
From: LI, YAN; HUBRIS, ALEXANDER; ZHONG, HAO
To: LSI CORPORATION
Reel/Frame 029638/0558 →