FLASH MEMORY READ ERROR RATE REDUCTION
An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.
1 . An apparatus comprising:
a first circuit configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust said reference voltage based on a plurality of parameters to lower an error rate in a second read of said set from said memory circuit; and
a second circuit configured to update said parameters in response to an error correction applied to said set after said first read from said memory circuit, wherein said memory circuit is configured to store said data in a nonvolatile condition by adjusting a plurality of threshold voltages.
2 . The apparatus according to claim 1 , wherein (i) said memory circuit comprises a flash memory and (ii) said parameters corresponding to said set track (a) a drift of a mean voltage among said threshold voltages in said set and (b) a spread of said threshold voltages about said mean voltage in said set.
3 . The apparatus according to claim 1 , further comprising a third circuit configured to generate a plurality of statistics as part of said error correction of said set, wherein said second circuit updates said parameters based on said statistics.
4 . The apparatus according to claim 1 , wherein said set is read in response to a read request received from a host.
5 . The apparatus according to claim 1 , wherein (i) an address space of said memory circuit comprises a plurality of groups, (ii) each of said groups comprises one of (a) a die, (b) a block, (c) a word line and (d) a page and (iii) said set is stored within one of said groups.
6 . The apparatus according to claim 5 , wherein said parameters corresponding to each of said groups are updated separately.
7 . The apparatus according to claim 1 , wherein (i) said memory circuit comprises a plurality of cells and (ii) each of said cells stores a plurality of bits in four or more states.
8 . The apparatus according to claim 7 , wherein said second circuit is further configured to extrapolate said parameters corresponding two or more of said states based on changes in said parameters corresponding a middle two of said states.
9 . The apparatus according to claim 1 , further comprising a third circuit configured to (i) perform said error correction and (ii) adjust said error correction using said parameters.
10 . The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
11 . A method for memory read error rate reduction, comprising the steps of:
(A) generating a reference voltage used by a memory circuit in a first read of a set of data, wherein said memory circuit is configured to store said data in a nonvolatile condition by adjusting a plurality of threshold voltages;
(B) updating a plurality of parameters in response to an error correction applied to said set after said first read from said memory circuit; and
(C) adjusting said reference voltage based on said parameters to lower an error rate in a second read of said set from said memory circuit.
12 . The method according to claim 11 , wherein (i) said memory circuit comprises a flash memory and (ii) said parameters corresponding to said set track (a) a drift of a mean voltage among said threshold voltages in said set and (b) a spread of said threshold voltages about said mean voltage in said set.
13 . The method according to claim 11 , further comprising the step of:
generating a plurality of statistics as part of said error correction of said set, wherein said parameters are updated based on said statistics.
14 . The method according to claim 11 , wherein said set is read in response to a read request received from a host.
15 . The method according to claim 11 , wherein (i) an address space of said memory circuit comprises a plurality of groups, (ii) each of said groups comprises one of (a) a die, (b) a block, (c) a word line and (d) a page and (iii) said set is stored within one of said groups.
16 . The method according to claim 15 , wherein said parameters corresponding to each of said groups are updated separately.
17 . The method according to claim 11 , wherein (i) said memory circuit comprises a plurality of cells and (ii) each of said cells stores a plurality of bits in four or more states.
18 . The method according to claim 17 , further comprising the step of:
extrapolating said parameters corresponding two or more of said states based on changes in said parameters corresponding a middle two of said states.
19 . The method according to claim 11 , further comprising the step of:
adjusting said error correction using said parameters.
20 . An apparatus comprising:
means for generating a reference voltage used by a memory circuit in a first read of a set of data, wherein said memory circuit is configured to store said data in a nonvolatile condition by adjusting a plurality of threshold voltages;
means for updating a plurality of parameters in response to an error correction applied to said set after said first read from said memory circuit; and
means for adjusting said reference voltage based on said parameters to lower an error rate in a second read of said set from said memory circuit.