Cross-decoding for non-volatile storage
View Patent ↗Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used.
1. A method comprising:
allocating storage space of one or more flash memories respectively to redundancy and data information;
wherein the flash memories have a plurality of cells each enabled to store a plurality of bits, the bits of the cells organized into respective pages corresponding to read/write quanta of the flash memories; and
wherein the allocating comprises configuring respective ratios of redundancy and data information to each of the pages such that an effective error rate of a first one of the pages corresponding to a first one of the bits of a first one of the cells approaches an effective error rate of a second one of the pages corresponding to a second one of the bits of the first one of the cells.
2. The method of claim 1 , wherein the effective error rates include effects of cross-decoding of the first and the second pages with respect to each other.
3. The method of claim 1 , wherein the respective ratios are in accordance with one or more of differing coding rates and techniques.
4. The method of claim 1 , further comprising interfacing requests to access the flash memories with a computing host.
5. The method of claim 4 , wherein the interfacing is compatible with a storage interface standard.
6. The method of claim 5 , wherein the storage interface standard comprises one or more of:
a Universal Serial Bus (USB) interface standard,
a Compact Flash (CF) interface standard,
a MultiMediaCard (MMC) interface standard,
a Secure Digital (SD) interface standard,
a Memory Stick interface standard,
an xD-picture card interface standard,
an Integrated Drive Electronics (IDE) interface standard,
a Serial Advanced Technology Attachment (SATA) interface standard,
an external SATA (eSATA) interface standard,
a Small Computer System Interface (SCSI) interface standard,
a Serial Attached Small Computer System Interface (SAS) interface standard,
a Fibre Channel interface standard, an Ethernet interface standard, and
a Peripheral Component Interconnect express (PCie) interface standard.
7. The method of claim 5 , wherein the computing host comprises one or more of:
a computer,
a workstation computer,
a server computer,
a storage server,
a Personal Computer (PC),
a laptop computer,
a notebook computer,
a netbook computer,
a Personal Digital Assistant (PDA),
a media player,
a media recorder,
a digital camera,
a cellular handset,
a cordless telephone handset, and
an electronic game.
8. The method of claim 1 , further comprising interfacing the flash memories.
9. The method of claim 8 , wherein the interfacing is at least in part via a flash memory interface.
10. A non-transitory computer readable medium having a set of instructions stored therein that when executed by a processing element cause the processing element to perform operations comprising:
allocating storage space of one or more flash memories respectively to redundancy and data information;
wherein the flash memories have a plurality of cells each enabled to store a plurality of bits, the bits of the cells organized into respective pages corresponding to read/write quanta of the flash memories; and
wherein the allocating comprises configuring respective ratios of redundancy and data information to each of the pages such that an effective error rate of a first one of the pages corresponding to a first one of the bits of a first one of the cells approaches an effective error rate of a second one of the pages corresponding to a second one of the bits of the first one of the cells.
11. The non-transitory computer readable medium of claim 10 , wherein the effective error rates include effects of cross-decoding of the first and the second pages with respect to each other.
12. The non-transitory computer readable medium of claim 10 , wherein the respective ratios are in accordance with one or more of differing coding rates and techniques.
13. The non-transitory computer readable medium of claim 10 , wherein the operations further comprise interfacing requests to access the flash memories with a computing host.
14. The non-transitory computer readable medium of claim 13 , wherein the interfacing is compatible with a storage interface standard.
15. The non-transitory computer readable medium of claim 14 , wherein the storage interface standard comprises one or more of:
a Universal Serial Bus (USB) interface standard,
a Compact Flash (CF) interface standard,
a MultiMediaCard (MMC) interface standard,
a Secure Digital (SD) interface standard,
a Memory Stick interface standard,
an xD-picture card interface standard,
an Integrated Drive Electronics (IDE) interface standard,
a Serial Advanced Technology Attachment (SATA) interface standard,
an external SATA (eSATA) interface standard,
a Small Computer System Interface (SCSI) interface standard,
a Serial Attached Small Computer System Interface (SAS) interface standard,
a Fibre Channel interface standard,
an Ethernet interface standard, and
a Peripheral Component Interconnect express (PCie) interface standard.
16. The non-transitory computer readable medium claim 13 , wherein the computing host comprises one or more of:
a computer,
a workstation computer,
a server computer,
a storage server,
a Personal Computer (PC),
a laptop computer,
a notebook computer,
a netbook computer,
a Personal Digital Assistant (PDA),
a media player,
a media recorder,
a digital camera,
a cellular handset,
a cordless telephone handset, and
an electronic game.
17. The non-transitory computer readable medium of claim 10 , wherein the operations further comprise interfacing the flash memories.
18. The non-transitory computer readable medium of claim 17 , wherein the interfacing is at least in part via a flash memory interface.
19. A system comprising:
one or more flash memories; and
a controller configured to allocate storage space of the one or more flash memories respectively to redundancy and data information;
wherein the one or more flash memories have a plurality of cells each enabled to store a plurality of bits, the bits of the cells organized into respective pages corresponding to read/write quanta of the flash memories; and
wherein the controller is enabled to configure respective ratios of redundancy and data information to each of the pages such that an effective error rate of a first one of the pages corresponding to a first one of the bits of a first one of the cells approaches an effective error rate of a second one of the pages corresponding to a second one of the bits of the first one of the cells.
20. The system of claim 19 , wherein the effective error rates include effects of cross-decoding of the first and the second pages with respect to each other.