IP Library Granted Patent US 9,395,924
Granted Patent B2
US 9,395,924 · App. 14/158,827 · Granted Jul 19, 2016

Management of and region selection for writes to non-volatile memory

Inventors: Earl T Cohen (Oakland, CA); Timothy Lawrence Canepa (Los Gatos, CA)
Assignee: Seagate Technology LLC
G06F3/0619G06F3/064G06F3/0608G06F3/0616G06F3/0653G06F3/0679G06F12/0246G06F2212/1016G06F2212/1044G06F2212/7201G06F2212/7202G06F2212/7208G06F2212/7211
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Quick Facts
Patent No.
US 9,395,924
App. No.
14/158,827
Granted
Jul 19, 2016
Kind
B2
Abstract

Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data.

Claims (41)

1. A method comprising:

receiving, from a host, a write command and source information associated with write data of the write command, the source information indicating a Logical Block Address (LBA) corresponding to the write data;

determining a difference between a number of reads of the LBA and a number of writes of the LBA via a counter corresponding to the LBA;

selecting one of a plurality of regions of a Non-Volatile Memory (NVM) based at least in part on the determined difference; and

writing the write data to the selected region, and each of the plurality of regions is a managed portion of the NVM.

2. The method of claim 1 , further comprising incrementing the counter when writes to the LBA occur and decrementing the counter when reads to the LBA occur.

3. The method of claim 1 , further comprising tracking characteristics of accesses to a set of LBAs, the set of LBAs including the LBA.

4. The method of claim 1 , further comprising converting the LBA to an address of the NVM.

5. The method of claim 4 , further comprising associating a map entry with the counter.

6. The method of claim 1 , further comprising:

analyzing the write data to determine a characteristic of the write data; and

selecting the one of the plurality of regions of the NVM based at least in part on the determined characteristic.

7. The method of claim 6 , wherein the characteristic is the write data is compressible.

8. The method of claim 1 , further comprising:

receiving an indication from the host the write data is multi-media data; and

selecting the one of the plurality of regions of the NVM based at least in part on the received indication.

9. A system comprising:

a band management module configured to:

receive a write command from a host; and

receive source information associated with write data of the write command, the source information indicating a logical block address (LBA) corresponding to the write data, the band management module including:

a logical block address (LBA) counters array with a counter corresponding to the LBA, the counter configured to store a difference between a number of reads of the LBA and a number of writes of the LBA; and

a band selector configured to select one of a plurality of regions of a non-volatile memory (NVM) based at least in part on the difference; and

the system configured to store the write data to the selected region.

10. The system of claim 9 , further comprising the counter configured to increment a count based on writes to the LBA and decrement the count based on reads of the LBA.

11. The system of claim 9 , further comprising the LBA counters array configured to track characteristics of accesses to a set of LBAs, the set of LBAs including the LBA.

12. The system of claim 9 , further comprising a map module configured to convert the LBA to an address of the NVM and to provide an association of a map entry with the counter.

13. The system of claim 9 , further comprising a data analysis module configured to analyze the write data to determine a characteristic of the write data; and the band selector further configured to select the one of the plurality of regions of the NVM based at least in part on the determined characteristic.

14. The system of claim 13 , wherein the characteristic is that the write data is uncompressible.

15. The system of claim 9 , further comprising a hint unit configured to receive an indication from the host that the write data includes a log file; and the band selector further configured to select the one of the plurality of regions of the NVM based at least in part on the received indication.

16. A memory device including instructions that when executed by a processor, cause the processor to:

determine a difference between a number of reads of a storage location associated with a specific logical block address and a number of writes of the storage location via a counter corresponding to the specific logical block address;

select one of a plurality of regions of a non-volatile memory (NVM) based at least in part on the determined difference; and

write data intended for the specific logical block address of the storage location to the selected region.

17. The memory device of claim 16 further including instructions that when executed by a processor, cause the processor to increment the counter for each write to the storage location and decrement the counter for each read from the storage location.

18. The memory device of claim 16 further including instructions that when executed by a processor, cause the processor to:

analyze the data to determine a characteristic of the data; and

select one of the plurality of regions of the NVM based at least in part on the determined characteristic.

19. The memory device of claim 18 , wherein the characteristic is that the data is executable data.

20. The memory device of claim 16 further including instructions that when executed by a processor, cause the processor to:

receive an indication from a host that the data is read-only data, read-mostly data, write- only data, or write-mostly data; and

select one of the plurality of regions of the NVM based at least in part on the received indication.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0571 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2014
From: COHEN, EARL T.; CANEPA, TIMOTHY LAWRENCE
To: LSI CORPORATION
Reel/Frame 032358/0646 →
Continuity (2)
Provisional Application 61755442 · Jan 22, 2013
Related Publication 20140208007A1 · Jul 24, 2014