IP Library Granted Patent US 9,092,310
Granted Patent B2
US 9,092,310 · App. 13/855,116 · Granted Jul 28, 2015

Host command based read disturb methodology

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Quick Facts
Patent No.
US 9,092,310
App. No.
13/855,116
Granted
Jul 28, 2015
Kind
B2
Abstract

An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of the group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.

Claims (20)

1. An apparatus comprising:

a memory configured to process a plurality of read/write operations, the memory comprising a plurality of memory modules each having a size less than a total size of the memory; and

a controller configured to (i) determine if a read disturb has occurred, and (ii) if the read disturb has occurred, the controller (a) determines a size of a group of read/write operations, and (b) writes all of the group of read/write operations to one of the memory modules.

2. The apparatus according to claim 1 , wherein the controller determines the size of the group of the read/write operations by determining a head pointer and a tail pointer of the group of the read/write operations.

3. The apparatus according to claim 1 , wherein the controller determines a difference between (a) the size of the group of read/write operations and (b) the size of each of the memory modules.

4. The apparatus according to claim 3 , wherein the controller (a) determines if the difference is below a predetermined value and (b) writes all of the group of read/write operations to one of the memory modules.

5. The apparatus according to claim 1 , wherein the controller overrides a wear leveling protocol.

6. The apparatus according to claim 1 , wherein the apparatus comprises a solid state drive (SSD).

7. A method for implementing a read disturb routine in a solid state drive (SSD) comprising a plurality of memory modules, comprising the steps of:

(A) determining if a read disturb has occurred;

(B) if the read disturb has not occurred, using unmodified read commands;

(C) if the read disturb has occurred, determining a size of a group of read/write operations; and

(D) if the read disturb has occurred, writing all of the group of read/write operations to one of the memory modules.

8. The method according to claim 7 , wherein the size of the group of the read/write operations is determined by determining a head pointer and a tail pointer of the group of the read/write operations.

9. The method according to claim 8 , wherein step (D) writes all of the read/write operations to one of the memory modules if the size of the memory module is greater than a size of the group of read/write operations.

10. An apparatus for implementing a read disturb routine in a solid state drive (SSD) comprising a plurality of memory modules, comprising:

means for determining if a read disturb has occurred;

means for using unmodified read commands if the read disturb has not occurred;

means for determining a size of a group of read/write operations if the read disturb has occurred; and

means for writing all of the group of read/write operations to one of the memory modules if the read disturb has occurred.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0272 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2013
From: ZHANG, ZHIQING; CHEN, YUAN; TAN, YUN SHUN; DUAN, XING HUI; CHEN, LIN FENG
To: LSI CORPORATION
Reel/Frame 030131/0432 →