Systems and methods for inter-cell interference mitigation in a flash memory

1. A data processing system, the data processing system comprising:

a soft information correction circuit operable to:

receive soft information corresponding to a series of voltage levels accessed from a block of memory cells;

calculate an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information; and

calculate corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value.

2. The data processing system of claim 1 , wherein the data processing system further comprises:

a data decoder circuit operable to apply a data decoding algorithm to the corrected soft information to yield a data output.

3. The data processing system of claim 2 , wherein the data decoder circuit is a low density data decoder circuit.

4. The data processing system of claim 1 , wherein calculating the corrected soft information is based at least in part on both the variance and a median of the soft information.

5. The data processing system of claim 4 , wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the variance and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

6. The data processing system of claim 4 , wherein the variance includes a left side variance and a right side variance, and wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the right side variance, the left side variance, and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

7. The data processing system of claim 1 , wherein the soft information is a probability that the voltage levels accessed from a block of memory cells are correct.

8. The data processing system of claim 7 , wherein the soft information is log likelihood information.

9. The data processing system of claim 1 , wherein the system is implemented as an integrated circuit.

10. The data processing system of claim 1 , wherein the data processing system is incorporated in a storage device comprising:

a block of flash memory cells, wherein the block of memory cells are a subset of the block of flash memory cells.

11. The data processing system of claim 10 , wherein each of the flash memory cells are multi-bit memory cells.

12. The data processing system of claim 11 , wherein the multi-bit memory cells are each capable of storing a voltage level representative of a number of bits, and wherein the number of bits is selected from a group consisting of: two bits, and three bits.

13. A method for accessing information from a storage device, the method comprising:

receiving, via a processor, soft information corresponding to a series of voltage levels accessed from a block of flash memory cells;

calculating, via the processor, an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information;

calculating, via the processor, corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value; and

applying, via the processor, a data decoding algorithm to the corrected soft information to yield a data output.

14. The method of claim 13 , wherein the data decoding algorithm is a low density parity check decoding algorithm.

15. The method of claim 13 , wherein calculating the corrected soft information is based at least in part on both the variance and a median of the soft information.

16. The method of claim 15 , wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the variance and the median; and calculating the corrected soft information based upon the offset reduced output and the median.

17. The method of claim 15 , wherein the variance includes a left side variance and a right side variance, and wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the right side variance, the left side variance, and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

18. The method of claim 13 , wherein the soft information is a probability that the voltage levels accessed from a block of memory cells are correct.

19. The method of claim 18 , wherein the soft information is log likelihood information.

20. A storage device, the storage device comprising:

a block of memory cells, wherein each of the memory cells is operable to store a voltage level representing two or more bits;

a soft information correction circuit operable to:

receive soft information corresponding to a series of voltage levels accessed from the memory cells;

calculate an offset reduced output of the received soft information by adding an offset value to the received soft information, the offset value being based on an estimated mean value and an estimated variance value associated with the soft information;

calculate corrected soft information by scaling the offset reduced output based on a scaling value derived from the estimated mean value; and

a data decoder circuit operable to apply a data decoding algorithm to the corrected soft information to yield a data output.