IP Library Granted Patent US 9,209,835
Granted Patent B2
US 9,209,835 · App. 14/135,837 · Granted Dec 8, 2015

Read retry for non-volatile memories

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Quick Facts
Patent No.
US 9,209,835
App. No.
14/135,837
Granted
Dec 8, 2015
Kind
B2
Abstract

An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Claims (32)

1. An apparatus for reading a non-volatile memory, comprising:

a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances;

a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values; and

a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

2. The apparatus of claim 1 , wherein the predetermined likelihood value constellation comprises a range of the likelihood values that is desired after mapping the read patterns to the likelihood values.

3. The apparatus of claim 1 , wherein the predetermined likelihood value constellation includes substantially an entire range of possible likelihood values.

4. The apparatus of claim 1 , wherein the likelihood generator comprises a lookup table correlating the read patterns to the likelihood values.

5. The apparatus of claim 1 , wherein the likelihood values comprise log likelihood ratios.

6. The apparatus of claim 1 , wherein the likelihood generator is operable to calculate the at least one other reference voltage based at least in part on the means and variances.

7. The apparatus of claim 1 , wherein the likelihood generator is operable to calculate the at least one other reference voltage based on the predetermined likelihood value constellation and not on spacings between the at least one reference voltage and the at least one other reference voltage.

8. The apparatus of claim 1 , wherein a number of entries in the predetermined likelihood value constellation is one greater than a total number of reference voltages used by the read controller.

9. The apparatus of claim 1 , further comprising a decoder operable to decode the likelihood values.

10. The apparatus of claim 9 , wherein the decoder comprises a min-sum low density parity check decoder.

11. The apparatus of claim 9 , wherein the tracking module, the likelihood generator, the read controller and the decoder are implemented as an integrated circuit.

12. The apparatus of claim 1 , further comprising a plurality of memory cells in the non-volatile memory.

13. The apparatus of claim 1 , wherein the non-volatile memory comprises a flash memory.

14. A method of reading data from a non-volatile memory, comprising:

calculating means and variances of a voltage distribution in the non-volatile memory;

calculating at least one secondary reference voltage at an offset to a first reference voltage based at least in part on the means and variances and on a set of target likelihood values;

reading the non-volatile memory using the first reference voltage and the at least one secondary reference voltage to yield a read pattern; and

mapping the read pattern to likelihood values.

15. The method of claim 14 , further comprising decoding the likelihood values to identify correct values of the data in the non-volatile memory.

16. The method of claim 15 , further comprising repeatedly performing retry reads when the decoding fails, and calculating at least one more secondary reference voltage for each successive retry read.

17. The method of claim 14 , wherein the set of target likelihood values comprise predetermined log likelihood ratios.

18. The method of claim 14 , wherein the at least one secondary reference voltage is calculated so that the read pattern will map to likelihood values substantially filling a range of all possible likelihood values.

19. The method of claim 14 , wherein the at least one secondary reference voltage is not calculated based on a uniform spacing of the first reference voltage and the at least one secondary reference voltage.

20. A non-volatile memory comprising:

a plurality of memory cells;

a tracking module operable to calculate means and variances of at least one voltage distribution in the memory cells and to calculate a first reference voltage;

a likelihood generator operable to calculate at least one secondary reference voltage based on the means and variances and on a set of target likelihood values and operable to map read patterns from the memory cells to likelihood values;

a read controller operable to read the read patterns from the memory cells using the first reference voltage and the at least one secondary reference voltage; and

a decoder operable to decode the likelihood values.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034773/0535 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS INCLUDED IN SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Nov 6, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034177/0257 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2014
From: ALHUSSIEN, ABDELHAKIM S.; HARATSCH, ERICH F.; SANKARANARAYANAN, SUNDARARAJAN; WU, YINGQUAN
To: LSI CORPORATION
Reel/Frame 031870/0976 →